toolflow¶
A python-based toolflow to build a vivado project from a simulink design, using the CASPER xps library.
A work in progress.
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class
toolflow.
ISEBackend
(plat=None, compile_dir='/tmp')[source]¶ -
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add_compile_cmds
(cores=8, plat=None)[source]¶ add the tcl commands for compiling the design, and then launch vivado in batch mode
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static
format_const
(attribute, val, port, index=None)[source]¶ Generate a tcl syntax command from an attribute, value and port (with indexing if required)
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class
toolflow.
SimulinkFrontend
(compile_dir='/tmp', target='/tmp/test.slx')[source]¶ -
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compile_user_ip
(update=False)[source]¶ Compile the users simulink design. The resulting netlist should end up in the location already specified in the peripherals file.
Parameters: update (bool) – Update the simulink model before running system generator
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class
toolflow.
Toolflow
(frontend='simulink', compile_dir='/tmp', frontend_target='/tmp/test.slx', jobs=8)[source]¶ A class embodying the main functionality of the toolflow. This class is responsible for generating a complete top-level verilog description of a project from a ‘peripherals file’ which encodes information about which IP a user wants instantiated.
The toolflow class can parse such a file, and use it to generate verilog, a list of source files, and a list of constraints. These can be passed off to a toolflow backend to be turned into some vendor-specific platform and compiled. At least, that’s the plan…
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__init__
(frontend='simulink', compile_dir='/tmp', frontend_target='/tmp/test.slx', jobs=8)[source]¶ Initialize the toolflow.
Parameters: - frontend (str) – Name of the toolflow frontend to use.
Currently only
simulink
is supported - compile_dir – Compile directory where build files and logs should go.
- frontend (str) – Name of the toolflow frontend to use.
Currently only
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build_top
()[source]¶ Copies the base top-level verilog file (which is platform dependent) to the compile directory. Constructs an associated VerilogModule instance ready to be modified.
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check_attr_exists
(thing, generator)[source]¶ Lots of methods in this class require that certain attributes have been set by other methods before proceeding. This is probably a symptom of the code being terribly structured. This method checks if an attribute exists and throws an error message if not. In principle it could automatically run the necessary missing steps, but that seems pretty suspect.
Parameters: - thing (str) – Attribute to check.
- generator (str) – Method which can be used to set thing (used for error message only)
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constraints_rule_check
()[source]¶ Check pin constraints against top level signals. Warn about missing constraints.
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dump_castro
(filename)[source]¶ Build a ‘standard’ Castro object, which is the interface between the toolflow and the backends.
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exec_flow
(gen_per=True, frontend_compile=True)[source]¶ Execute a compile.
Parameters: - gen_per (bool) – Have the toolflow frontend generate a fresh peripherals file
- frontend_compile (bool) – Run the frontend compiler (eg. System Generator)
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gen_periph_objs
()[source]¶ Generate a list of yellow blocks from the current peripheral file.
Internally, calls:
_parse_periph_file
: parses .per file_extract_plat_info
: instantiates platform instance
Then calls each yellow block’s constructor. Runs a system-wide drc before returning.
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generate_consts
()[source]¶ Compose a list of constraints from each yellow block. Use platform information to generate the appropriate physical realisation of each constraint.
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generate_hdl
()[source]¶ Generates a top file for the target platform based on the peripherals file.
Internally, calls:
instantiate_periphs
: call each yellow block’s mod_top methodinstantiate_user_ip
: add ports to top module based on port entries in peripheral fileregenerate_top
: rewrite top.v
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generate_xml_ic
(memory_map)[source]¶ Generate xml interconnect file that represent top-level AXI4-Lite interconnect for Oxford’s xml2vhdl.
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generate_xml_memory_map
(memory_map)[source]¶ Generate xml memory map files that represent each AXI4-Lite interface for Oxford’s xml2vhdl.
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regenerate_top
()[source]¶ Generate the verilog for the modified top module. This involves computing the wishbone interconnect / addressing and generating new code for yellow block instances.
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xml2vhdl
()[source]¶ Function to call Oxford’s python code to generate AXI4-Lite VHDL register interfaces from an XML memory map specification.
Obtained from: https://bitbucket.org/ricch/xml2vhdl/src/master/
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class
toolflow.
ToolflowBackend
(plat=None, compile_dir='/tmp')[source]¶ -
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add_const_file
(constfile)[source]¶ Add a constraint file to the project. via a tcl incantation. In non-project mode, it is important to note that copies are not made of files. The files are read from their source directory. Project mode copies files from their source directory and adds them to the a new compile directory.
Parameters: constfile –
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add_source
(source, plat)[source]¶ Add a sourcefile to the project. Via a tcl incantation. In non-project mode, it is important to note that copies are not made of files. The files are read from their source directory. Project mode copies files from their source directory and adds them to the a new compile directory.
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static
calculate_checksum_using_bitstream
(bitstream, packet_size=8192)[source]¶ Summing up all the words in the input bitstream, and returning a
Checksum
- Assuming that the bitstream HAS NOT been padded yetParameters: - bitstream – The actual bitstream of the file in question
- packet_size – max size of image packets that we pad to
Returns: checksum
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gen_constraint_file
(constraints)[source]¶ Pass this method a toolflow-standard list of constraints which have already had their physical parameters calculated and it will generate a constraint file and add it to the current project.
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mkfpg
(filename_bin, filename_fpg)[source]¶ This function makes the fpg file header and the final fpg file, which consists of the fpg file header (core_info.tab, design_info.tab and git_info.tab) and the compressed binary file. The fpg file is used to configure the ROACH, ROACH2, MKDIG and SKARAB boards.
Parameters: - filename_bin (str) – This is the path and binary file (top.bin) that contains the FPGA programming data.
- filename_fpg (str) – This is the output time stamped fpg file name
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class
toolflow.
ToolflowFrontend
(compile_dir='/tmp', target='/tmp/test.slx')[source]¶ -
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compile_user_ip
()[source]¶ Compile the user IP to a single HDL module.
Return the name of this module.
Should be overridden by each FrontEnd subclass.
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gen_periph_file
(fname='jasper.per')[source]¶ Call upon the frontend to generate a jasper-standard file defining peripherals (yellow blocks) present in a model.
This method should be overridden by the specific frontend of choice, and should return the full path to the peripheral file.
Use
skip = True
to just return the name of the file, without bothering to regenerate it (useful for debugging, and future use cases where a user only wants to run certain steps of a compile)
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class
toolflow.
VivadoBackend
(plat=None, compile_dir='/tmp', periph_objs=None)[source]¶ -
__init__
(plat=None, compile_dir='/tmp', periph_objs=None)[source]¶ Parameters: - plat –
- compile_dir –
- periph_objs –
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add_compile_cmds
(cores=8, plat=None, synth_strat=None, impl_strat=None)[source]¶ Add the tcl commands for compiling the design, and then launch vivado in batch mode
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add_const_file
(constfile)[source]¶ Add a constraint file to the project. via a tcl incantation. In non-project mode, it is important to note that copies are not made of files. The files are read from their source directory. Project mode copies files from their source directory and adds them to the a new compile directory.
Parameters: constfile –
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add_source
(source, plat)[source]¶ Add a sourcefile to the project. Via a tcl incantation. In non-project mode, it is important to note that copies are not made of files. The files are read from their source directory. Project mode copies files from their source directory and adds them to the a new compile directory.
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add_tcl_cmd
(cmd, stage='pre_synth')[source]¶ Add a command to the tcl command list with a trailing newline.
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compile
(cores, plat, synth_strat=None, impl_strat=None)[source]¶ Parameters: - cores –
- plat –
- impl_strat – Implementation Strategy to use when carrying out the implementation run ‘impl’
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static
format_cfg_const
(attribute, val)[source]¶ Generate a configuration tcl syntax command from an attribute and value
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static
format_const
(attribute, val, port, index=None)[source]¶ Generate a tcl syntax command from an attribute, value and port (with indexing if required)
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gen_add_compile_dir_source_tcl_cmds
()[source]¶ Run each blocks add_compile_dir_source functions and add them to the projects sources
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gen_constraint_file
(constraints)[source]¶ Pass this method a toolflow-standard list of constraints which have already had their physical parameters calculated and it will generate a constraint file and add it to the current project.
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gen_yellowblock_custom_hdl
()[source]¶ Create each yellowblock’s custom hdl files and add them to the projects sources
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gen_yellowblock_tcl_cmds
()[source]¶ Compose a list of tcl commands from each yellow block. To be added to the final tcl script.
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