CASPER Tutorials
0.1

SNAP Tutorials

  • Tutorial 1: Introduction to Simulink
    • Creating Your Design
      • Create a New Model
      • Library organization
      • Add Xilinx System Generator and XSG core config blocks
      • Flashing LED
        • Add a counter
        • Add a slice block to select out the msb
        • Add a GPIO block
        • Add a terminator
        • Connect your design
        • Software control
        • Add the software registers
        • Add the counter
        • Add the slice blocks
        • Connect it all up
      • Adder
        • Add the software registers
        • Add the adder block
        • Add the scope and simulation inputs
        • Connect it all together
    • Simulating
    • Compiling
      • Advanced Compiling
    • Programming the FPGA
    • Conclusion
  • Tutorial 2: 10GbE Interface
    • Introduction
    • Background
    • Create a new model
      • Add reset logic
        • Add a software register
        • Add Goto blocks
      • Add 10GbE and associated registers for data transmission
        • Add a 10GbE block for data transmission
        • Add registers to provide the target IP address and port number
      • Create a subsystem to generate a counter to transmit as data
      • Construct a subsystem for data generation logic
      • Add a counter to generate a certain amount of data
      • Add a counter to limit the data rate
      • Finalise logic including counter to be used as data
      • Receive blocks and logic
      • Buffers to capture received and transmitted data
      • LEDs and status registers
    • Compilation
      • Programming and interacting with the FPGA
    • Conclusion
  • Tutorial 3: Wideband Spectrometer
    • Introduction
    • Setup
    • Spectrometer Basics
    • Simulink / CASPER Toolflow
      • Simulink Design Overview
      • adc
      • pfb_fir_real
      • fft_wideband_real
      • power
      • quant
      • simple_bram_vacc
      • Even and Odd BRAMs
      • Software Registers
    • Configuration and Control
      • Hardware Configuration
      • The snap_tut_spec.py spectrometer script
      • iPython walkthrough
    • Conclusion
  • Tutorial 4: Wideband Pocket Correlator
    • Introduction
    • Background
      • Interferometry
      • Correlation
      • Polarization
      • The Correlator
    • Creating Your Design
      • Create a new model
      • System Generator and Platform Blocks
      • Sync Generator
      • ADCs
      • Control Register
      • Clip Detect and status reporting
      • PFBs, FFTs and Quantisers
      • LEDs
      • ADC RMS
      • The MAC operation
    • Software
  • Yellow Block Tutorial: Bidirectional GPIO
    • 1. Making a Bidirectional GPIO - HDL (Verilog)
    • 2. Making a Bidirectional GPIO - Simulink
    • Am I on the right track?
    • Python auto-gen scripts (JASPER Toolflow)
    • Testing
    • Add yellow block to XPS Library

SKARAB Tutorials

  • Tutorial 1: Introduction to Simulink
    • Creating Your Design
      • Create a New Model
      • Library organization
      • Add Xilinx System Generator and XSG core config blocks
      • Add an Ethernet core block
      • Flashing LED
        • Add a counter
        • Add a slice block to select out the msb
        • Add a GPIO block
        • Add a terminator
        • Connect your design
        • Software control
        • Add the software registers
        • Add the counter
        • Add the slice blocks
        • Connect it all up
      • Adder
        • Add the software registers
        • Add the adder block
        • Add the scope and simulation inputs
        • Connect it all together
    • Simulating
    • Compiling
      • Advanced Compiling
    • Programming the FPGA
    • Conclusion
  • Tutorial 2: 40GbE Interface
    • Introduction
    • Background
    • Tutorial Outline
    • Tx Design
    • Rx Design
    • Running the python script
      • Script arguments
  • Tutorial 3: HMC Interface
    • Introduction
    • Background
    • Create a new model
      • Add control and reset logic
        • Add a software register
        • Add Goto Blocks
      • Add a write and read counter to generate test data for the HMC
        • Add Counter Blocks
        • Add Delay Blocks
        • Add Goto and From Blocks
        • Add Gateway Out Blocks and Scopes
      • Add functionality to control the write and read data rate
        • Add a Counter Block
        • Add Xilinx Constant Blocks
        • Add Slice Block
        • Add From Blocks
        • Add Xilinx Convert (cast) Block
        • Add Xilinx Bus Multiplexer (Mux) Block
        • Add Xilinx Logical Block
        • Add Gateway Out and To Workspace Block (Optional)
      • Add HMC and associated registers for error monitoring
        • Add the HMC yellow block for memory accessing
        • Add a register to provide HMC status monitoring
      • Implement the HMC reordering functionality
      • Buffers to capture HMC write, HMC read and HMC reordered read data
      • HMC status registers
        • Write status registers
        • Read status registers
    • Simulink Simulation
    • Compilation
    • Programming the FPGA
      • Analysing the Display Data
        • Other notes
    • Conclusion
  • Tutorial 4: Wideband Spectrometer
    • Tutorial 4: Wideband Spectrometer - DDC Mode
      • Introduction
      • Setup
      • Spectrometer Basics
      • Simulink / CASPER Toolflow
        • Simulink Design Overview
        • adc
        • fft
        • power
        • simple_bram_vacc
        • Software Registers
      • Configuration and Control
        • Hardware Configuration
        • The tut_spec.py spectrometer script
      • Conclusion
    • Tutorial 4: Wideband Spectrometer - Bypass Mode
      • Preface
      • Introduction
      • Setup
      • Spectrometer Basics
      • Simulink / CASPER Toolflow
        • Simulink Design Overview
        • adc
        • fft
        • power
        • simple_bram_vacc
        • Software Registers
      • Configuration and Control
        • Hardware Configuration
        • The tut_spec_byp.py spectrometer script
      • Conclusion
  • Tutorial 5: SKARAB ADC Synchronous Data Acquisition
    • Tutorial 5 [latest]: SKARAB ADC Synchronous Data Acquisition
      • Introduction
      • SKARAB ADC Board Overview
      • SKARAB ADC Hardware Setup
      • SKARAB ADC Yellow Block
        • Overview
        • Master and Slaves
        • Description of DDC Mode SKARAB ADC Yellow Block (skarab_adc4x3g_14)
        • Description of Bypass Mode SKARAB ADC Yellow Block (skarab_adc4x3g_14_byp)
      • Simulink Design Clocking Considerations
      • Example Designs
      • SKARAB ADC Firmware Version Requirements
      • CASPER Toolflow and casperfpga Library Requirements
      • Test Procedure
    • Tutorial 5 [previous]: 2.8 GSPS, N-channel, Synchronous Data Acquisition
      • Introduction
      • Simulink Design Overview
      • SKARAB_ADC4X3G14_BYP Yellow Block Description
      • SKARAB Yellow Block Clocking
      • Usage Instructions

Red Pitaya Tutorials

  • Guide to Setting Up Your New Red Pitaya
    • Running the script on a preloaded RP SD Card
  • Tutorial 1: Introduction to Simulink
    • Creating Your Design
      • Create a New Model
      • Library organization
      • Add Xilinx System Generator and XSG core config blocks
      • Flashing LED
        • Add a counter
        • Add a slice block to select out the msb
        • Add a GPIO block
        • Add a terminator
        • Connect your design
        • Software control
        • Add the software registers
        • Add the counter
        • Add the slice blocks
        • Connect it all up
      • Adder
        • Add the software registers
        • Add the adder block
        • Add the scope and simulation inputs
        • Connect it all together
    • Simulating
    • Compiling
      • Advanced Compiling
    • Programming the FPGA
    • Conclusion
  • Tutorial 2 : ADC and DAC Interface
    • Introduction
    • Required Equipment
    • Background
    • Create a new model
      • Add Reset logic
        • Add a software register
        • Add Goto Block
        • Add Edge_Detect block
      • Add ADC and associated registers and gpio for debugging
        • Add the ADC yellow block for digital to analog interfacing
        • Add registers and gpio to provide ADC debugging
      • Add DAC
        • Add the DAC yellow block for digital to analog interfacing
      • Buffers to capture ADC Data Valid, ADC Channel 1 and ADC Channel 2
    • Compilation
    • Programming the FPGA (Zynq PL)
      • Analysing the Display Data
      • Bonus Challenge
        • Other notes
    • Conclusion
  • Tutorial 3: Wide(-ish)band Spectrometer
    • Introduction
    • Setup
    • Spectrometer Basics
    • Simulink / CASPER Toolflow
      • Simulink Design Overview
      • adc
      • Xilinx FFT
      • power
      • simple_bram_vacc
      • Snap Blocks
      • Software Registers
    • Configuration and Control
      • Hardware Configuration
      • The tut_spec.py spectrometer script
    • Conclusion

RFSoC Tutorials

  • CASPER RFSoC README
    • Introduction
    • The RFSoC
    • Platforms
    • Tutorials
      • Links
      • Designs
  • Getting Started With RFSoC
    • Introduction
    • Environment Setup
      • Pre requisites
    • Core Setup
      • Toolflow Setup
      • Platform Processor System Setup
      • Setup Casperfpga
    • Misc. Configuration
      • Platform Network Configuration
      • Manually Writing Platform MAC Address
  • Tutorial 1: RFSoC Platform Yellow Block and Simulink Overview
    • Creating Your First Design
      • Create a New Model
      • Library Organization
      • Add the Xilinx System Generator and CASPER Platform blocks
      • The Example Design
      • Function 1: Flashing LED
        • Step 1: Add a counter
        • Step 2: Add a slice block to select the MSB
        • Step 3: Add a GPIO Block
        • Step 4: Add a terminator
        • Step 5: Connect the design
      • Function 2: Software Controllable Counter
        • Step 1: Add the software registers
        • Step 2: Add the counter
        • Step 3: Add the slice blocks
        • Step 4: Connect the design
      • Function 3: Software Controllable Adder
        • Step 1: Add the software registers
        • Step 2: Add the adder block
        • Step 3: Add the scope and simulation inputs
        • Step 4: Connect the design
        • Extra Design Function (RFSoC2x2 only)
      • Simulating the design
    • Compiling
    • Programming the FPGA
      • Step 1: Copy the .fpg file to where you need it
      • Step 2: Connect to the board
    • Interacting with the board
    • Conclusion
  • Tutorial 2: The RFDC Interface
    • Introduction
    • The Example Design
      • Step 1: Add the XSG and RFSoC platform yellow block
      • Step 2: Place and configure the RFDC yellow block
      • Step 3: Update the platform yellow block
      • Step 4: Place and configure the Snapshot blocks
      • Step 5: Validate the design
      • Step 6: Build!
    • Testing the Design
    • Conclusion
  • Tutorial 3: The RFDC DAC Interface
    • Introduction
    • The Loopback Design
      • Section 1: Assembling & Configuring the blocks
        • Add your System Generator and RFSoC 4x2 blocks
        • Add your rfdc block
        • Add your software_register blocks
        • Add your delay block
      • Section 2: Hardware Test
    • The Waveform Generator Design
      • Section 1: Assembling & Configuring the blocks
        • Add your System Generator and RFSoC 4x2 blocks
        • Add your rfdc block
        • Add your shared_bram block
        • Add your munge block
        • Add your Counter block
        • Add some Constant blocks
        • Add your Enable software_register block
        • Add a waveform length wf_len register
      • Section 2: Generating your signal
      • Section 3: Sending your signal out
      • Errors
  • Tutorial 3: Example Spectrometer
    • Introduction
    • Setup
    • Spectrometer Basics
    • Simulink / CASPER Toolflow
      • Simulink Design Overview
      • RFDC
      • Munge blocks
      • Polyphase FIRs
      • CASPER FFTs
      • Power
      • Sync Gen
      • Vector Accumulator
      • Shared BRAMs
      • Software Registers
    • Configuration and Control
      • Hardware Configuration
      • Python
    • Conclusion
  • Tutorial 4: 100GbE
    • Introduction
      • Prerequisites and Common Troubleshooting
    • Simulink / CASPER Toolflow
      • Part 1: Testing the 100GbE yellow block
      • 100 GbE Yellow Block
      • Observing Packets at the NIC
      • Part 2: Streaming from the RFDC
      • RFDC
      • Munge blocks
      • Packetizer
    • Simple Packet Capture and Processing with Python
      • Script Overview
      • Running the Scripts
    • Conclusion
    • Appendix and Reference
      • Memory Map and Software Programmable Interface

Documentation

  • CASPER Documentation
  • AXI Documentation
  • Block Documentation
  • The CASPER Toolflow
  • Toolflow Sourcecode
  • casperfpga Sourcecode

ROACH Tutorials

  • Tutorial 1: Introduction to Simulink
    • Creating Your Design
      • Create a New Model
      • Library organization
      • Add Xilinx System Generator and XSG core config blocks
      • Flashing LED
        • Add a counter
        • Add a slice block to select the MSB
        • Add a GPIO block
        • Add a terminator
        • Connect your design
        • Software control
        • Add the software registers
        • Add the counter
        • Add the slice blocks
        • Connect it all up
      • Adder
        • Add the software registers
        • Add the adder block
        • Add the scope and simulation inputs
        • Connect it all together
    • Simulating
    • Compiling
    • Programming the FPGA
    • Conclusion
  • Tutorial 2: 10GbE Interface
    • Introduction
    • Background
    • Create a new model
      • Add reset logic
        • Add a software register
        • Add Goto blocks
      • Add 10GbE and associated registers for data transmission
        • Add a 10GbE block for data transmission
        • Add registers to provide the target IP address and port number
      • Create a subsystem to generate a counter to transmit as data
      • Construct a subsystem for data generation logic
      • Add a counter to generate a certain amount of data
      • Add a counter to limit the data rate
      • Finalise logic including counter to be used as data
      • Receive blocks and logic
      • Buffers to capture received and transmitted data
      • LEDs and status registers
    • Compilation
      • Programming and interacting with the FPGA
    • Conclusion
  • Tutorial 3: Wideband Spectrometer
    • Introduction
    • Setup
    • Spectrometer Basics
    • Simulink / CASPER Toolflow
      • Simulink Design Overview
      • adc
      • pfb_fir_real
      • fft_wideband_real
      • power
      • quant
      • simple_bram_vacc
      • Even and Odd BRAMs
      • Software Registers
    • Configuration and Control
      • Hardware Configuration
      • The tut3.py spectrometer script
      • iPython walkthrough
    • Conclusion
  • Tutorial 4: Wideband Pocket Correlator
    • Introduction
    • Background
      • Interferometry
      • Correlation
      • Polarization
      • The Correlator
    • Setup
    • Creating Your Design
      • Create a new model
      • System Generator and XSG Blocks
      • Sync Generator
      • ADCs
      • Control Register
      • Clip Detect and status reporting
      • PFBs, FFTs and Quantisers
      • LEDs
      • ADC RMS
      • The MAC operation
    • Software

Board Info

  • RFSoC 2x2
    • RF Clocking
    • ADC Inputs
  • RFSoC 4x2
    • RF Clocking
  • ZCU111
    • RF Clocking
  • ZCU208
    • RF Clocking
    • Notes
  • ZCU216
    • RF Clocking
  • HTG ZRF16
    • RF Clocking
    • Notes
      • Toolflow Compatability
      • LMK Dual Loop Mode
      • QA
CASPER Tutorials
  • Docs »
  • Search

© Copyright 2018, Collaboration for Astronomy Signal Processing and Electronics Research

Built with Sphinx using a theme provided by Read the Docs.