Programmable Fine Delay w/ Fringe stop¶
This block performs the fine delay correction along with the fringe stop. It accepts the simultaneous stream of data from the FFT module and has a run time programmable fine delay correction along with the fringe stopping.
Note: This block is specifically compatible with the “fft_wideband_real” module. For other FFT modules changes will be required in this block depending upon output of the FFT module used in the design.
|Number of simultaneous inputs||n_input||Number of simultaneous inputs (in frequency domain) from the FFT module.|
|Number of FFT channels||fft_len||Number of channels in the FFT|
|FFT input bitwidth||fft_bits||Number of bits in each real and imaginary samples obtained from the FFT module.|
|Sine-Cos LUT input bitwidth||theta_bits||Address bitwidth required for the SineCos LUT and hence decides the resolution of the phase. Allowable bitwidth for Sine-Cos LUT ranges from 3- 16.|
|Sine-Cos LUT output data width||sine_cos_bits||Data width of the sine cos LUT.|
|Maximum number of FFT cycles (Rate of change of fringe = 2^?)||fft_cycle_bits||Number of FFT cycles after which the rate of change of fringe needs to be applied. The number of FFT cycles are specified in terms of powers of 2.|
|sync||In||Boolean||Indicates the next clock cycle which contains valid data.|
|theta_fract||In||Unsigned||Sets the integer number required for fine delay correction.The bitwidth is equal to the address width for SineCos LUT. The method of calculating the range of integer required for the fine delay correction is explained in Description.|
|theta_fs||In||Unsigned||Sets the integer value equivalent to the initial phase value for fringe stop . The bitwidth is equal to the address width for SineCos LUT. Hence the possible range for initial phase varies from 0 to 2^theta_bits.|
|fft_fs||In||Unsigned||Sets the number of FFT cycles after which fringe update rate need to be applied.|
|en_theta_fs||In||Unsigned||This is the one bit control signal required to upload the new initial phase required for fringe stop. The new initial phase value gets loaded only at the posedge of this signal.|
|pol_in||In||Inherited||The frequency domain stream from the FFT module.|
|sync_out||Out||Boolean||Indicates that data out will be valid next clock cycle.|
|out||Out||Inherited||The fine delay and fringe stop corrected frequency channels.|
This block performs the fine delay correction along with the fringe stop. This block accepts the simultaneous stream of data from the FFT module and has a run time programmable fine delay correction along with the fringe stopping.
Note: This block is specifically compatible with the “fft_wideband_real” module. For other FFT modules changes will be required in this block depending upon the way in which the data is output from the FFT module.
Fine Delay Correction:
Masking parameters like theta_bits and sine_cos_bits decides the resolution of the phase required for fine delay and fringe stop.
For eg. theta_bits = 14 will generate a SineCos LUT with a depth of 2^14=16K, hence the resolution is of 0.02197 degrees. Consider the correlator design with specifications like bandwidth = 300MHz and no. of FFT channels = fft_len = 1024, then the maximum integer value of theta_fract (i.e. max fine delay = 1 clk cycle)will be x = (2^ theta_bits)/ (fft_len/2) = 32
Thus 1/32th of the clock cycle delay can be compensated with the above parameters.
Masking parameter fft_cycle_bits determines the maximum number of FFT cycles after which the fringe phase will be incremented.
For eg. Let the sync period is of 2^27 clks and number of FFT points be 2^10 then the maximum number of FFT cycles for incrementing the fringe phase by amount of resolution set for the Sine-Cos LUT = 2^27 / 2^10 = 2^17
It means that minimum rate of incrementing fringe phase by 0.02197 degrees is after 2^17 FFT cycles.