10 GbE Transceiver¶
This block sends and receives UDP frames (packets). It accepts a 64 bit wide data stream with user-determined frame breaks. The data stream is wrapped in a UDP frame for transmission. Incoming UDP packets are unwrapped and the data presented as a 64 bit wide stream.
|Port||port||Selects the physical CX4 port.|
|Shallow RX Fifo||rx_dist_ram||Selects shallow distributed RAM rather than BRAM for the RX FIFO. This option should only be used if the application clock is faster than 156.25 MHz. Constant overruns will most likely occur for clock frequency lower than this.|
|Pre-emphasis||pre_emph||Selects the default pre-emaphasis to use over the physical link. Currently unused.|
|Differential Swing||swing||Selects the size of the differential swing to use in mV. Currently unused.|
|Enable Fabric on Startup||fab_en||This will enable the 10Ge interface on start-up, negating the requirement of software intervention.|
|Fabric MAC Addresss||fab_mac||Sets the default MAC, usually configured by software.|
|Fabric IP Addresss||fab_ip||Sets the default IP, usually configured by software.|
|Fabric UDP Port||fab_port||Sets the default UDP Port, usually configured by software.|
|Fabric Gateway||fab_gate||Sets the default gateway address, usually configured by software.|
|Enable CPU RX||cpu_rx_en||Optionally disable the CPU receive interface to save 2 BRAMS, if that interface is not required.|
|Enable CPU TX||cpu_tx_en||Optionally disable the CPU trasmit interface to save 2 BRAMS, if that interface is not required.|
|rst||in||boolean||Resets the transmit and receive memories when asserted|
|tx_data||in||UFix_64_0||The data stream to be transmitted|
|tx_valid||in||boolean||The core accepts the data on
|tx_dest_ip||in||UFix_32_0||Selects the IP address of the receiving device|
|tx_dest_port||in||UFix_16_0||Selects the listening port of the receiving device (UDP port)|
|tx_end_of_frame||in||boolean||Signals the transceiver to begin transmitting the buffered frame (ie signals end of the frame). This signal must pulse high on the same clock cycle as the final tx_valid signal|
|rx_ack||in||boolean||Used to acknowledge reception of the data currently on rx_data and signals the transceiver to produce the next 64 bits from the receiver FIFO.|
|rx_overrun_ack||in||boolean||Used to reset the RX state machine when a RX overrun occurs.|
|led_up||out||boolean||Indicates a link on the port|
|led_rx||out||boolean||Represents received traffic on the port|
|led_tx||out||boolean||Represents transmitted traffic on the port|
|tx_afull||out||boolean||Indicates that the TX FIFO is almost full|
|tx_overflow||out||boolean||Indicates that the TX FIFO has overflowed|
|rx_data||out||UFix_64_0||The received data stream.|
|rx_valid||out||boolean||Indicates that the data on rx_data is valid (indicates a packet, or partial packet is in the RX buffer).|
|rx_source_ip||out||UFix_32_0||Represents the IP address of the sender of the current packet.|
|rx_source_port||out||UFix_16_0||Represents the sender’s UDP port of the current packet.|
|rx_end_of_frame||out||boolean||Goes high to indicate the end of the received frame.|
|rx_bad_frame||out||UFix_16_0||Indicates a CRC error on the frame immediately received when asserted simultaneously with
|rx_overrun||out||UFix_16_0||Indicates that an RX buffer overrun when asserted simultaneously with
This document is a draft and requires verification.
This core will typically be configured by software by setting the following OPB registers: MAC, IP, UDP port, ARP table, gateway and fabric enable. However, there are currently parameters to set these values (except for the ARP table) at build time.
To transmit, data is clocked into the TX buffer through
64 bit wide words using
tx_valid. When sending the final word of
data in the packet, simultaneously pulse the
the transceiver will add a UDP wrapper addressed to
tx_dest_ip:tx_dest_port and begin transmission immediately. Note
that tx_dest_ip and tx_dest_port are only looked at when
tx_end_of_frame is pulsed high, thus the value must be valid for that
clock period but is irrelevant otherwise.
The transmit FIFO can only handle frame sizes of up to 8704 bytes, or
1088 64 bit words. As the TX FIFO approaches full, the
signal will be asserted. This is an indication that the application
should stop entering data into the core. If the application overflows
the TX buffer, the
tx_overflow signal will be asserted. When the
overflow is asserted the TX interface will block, requiring a reset
rst) to return to full functionality.
Upon receipt of a packet,
rx_valid will go high, with the received
data presented on
rx_data in 64 bit wide words. You acknowledge
receipt of this data using
rx_ack, at which point the next data word
will be presented. When the end of the packet is reached,
rx_end_of_frame will go high. If the a CRC error occurred when
receiving the packet, the
rx_bad_frame signal will be asserted.
If the RX data overran the RX FIFO, the
rx_overrun signal will be
asserted along with
rx_end_of_frame. When this occurs the RX state
machine will block until the
rx_overrun_ack is asserted. It is
recommended that the
rx_overrun be directly connected to the
There is no hard maximum frame size for RX. However, care must be taken not to overrun the rx buffer.
To transmit, the IPv4 address is represented as a 32 bit binary number
(whereas it’s usually represented as four 8 bit decimal numbers). For
example, if you wanted to send all packets to
192.168.1.1, you would
as the IP address. The port is represented by a 16 bit number, allowing full addressing of the UDP port range. Ports below 1024 are generally reserved for Linux kernel and Internet functions. Ports 1024 - 49151 are registered for specific applications and may not be used without IANA registration. To ensure inter-operability and compatibility, we recommend using dynamic (private) ports 49152 through 65535.
The LED lines indicate port activity and can be connected to external GPIO LED interfaces. Bear in mind that even if no packets are being transmitted or received through the Simulink interface block, miscellaneous configuration packets are still sent and may be received by the microprocessor core. This activity will also be reflected on the activity LEDs.
Apart from configuring the block, the processor is also used to map the routing tables. ARP requests and responses are handled by the CPU.