Digitally mixes an input signal (which can be several samples in parallel) with an LO of the indicated frequency (which is some fraction of the native FPGA clock rate).
|The (power of 2) denominator of the mixing frequency.
|The numerator of the mixing frequency.
|Number of Parallel Streams
|The number of samples that arrive in parallel.
|The bitwidth of LO samples.
|The latency of sin/cos lookup table.
|The latency of mixing multipliers.
|Takes in an impulse the cycle before the
dins are valid.
|Input X to be mixed and output on
|This signal will be high the cycle before the data coming out is valid.
|Real output of mixed
|Imaginary output of mixed
Mixer mixes the incoming data and produces both real and imaginary
M and F must both be integers, and M must be a power of 2. The ratio F/M should equal the ratio f/r where r is the data rate of the sampled signal. For example, an F/M of 3/16 would downmix an 800Msps signal with an LO of 150MHz.