Digitally mixes an input signal (which can be several samples in parallel) with an LO of the indicated frequency (which is some fraction of the native FPGA clock rate).
|Frequency Divisions||freq_div||The (power of 2) denominator of the mixing frequency.|
|Mixing Frequency||freq||The numerator of the mixing frequency.|
|Number of Parallel Streams||nstreams||The number of samples that arrive in parallel.|
|Bit Width||n_bits||The bitwidth of LO samples.|
|BRAM Latency||bram_latency||The latency of sin/cos lookup table.|
|MULT Latency||mult_latency||The latency of mixing multipliers.|
|sync||IN||boolean||Takes in an impulse the cycle before the
|dinX||IN||Fix_8_7||Input X to be mixed and output on
|sync_out||OUT||boolean||This signal will be high the cycle before the data coming out is valid.|
|realX||OUT||Fix_(n_bits)_(n_bits-1)||Real output of mixed
|imagX||OUT||Fix_(n_bits)_(n_bits-1)||Imaginary output of mixed
Mixer mixes the incoming data and produces both real and imaginary
M and F must both be integers, and M must be a power of 2. The ratio F/M should equal the ratio f/r where r is the data rate of the sampled signal. For example, an F/M of 3/16 would downmix an 800Msps signal with an LO of 150MHz.