The x64_ADC block converts 64 analog inputs to digital outputs. Every clock cycle, the inputs are sampled and digitized to 12 bit binary point numbers in the range of [-1, 1).
|ADC clock rate (MHz)||adc_clk_rate||Sets the rate of the ADC sampling clock. The ROACH clock is derived from the ADC clock and should be 4x the clock rate entered here.|
|Include SPI interface?||spi||If checked, includes the ports and logic necessary to set the ADC control registers via SPI.|
|GPIO bank||ctrl_gpio||The ADC SPI and reset interfaces are not routed through the ZDOK connector. This parameter selects which of the ROACH GPIO banks to use to control them.|
|sim[0:15]||IN||double||sim<n> should be connected to analogue channels 4n:4n+3 to be digitized. Note: For simulation only.|
|sim_sync||IN||double||Input should be high when channel 4n is present on input sim<n>. Note: For simulation only.|
|adc_rst||IN||Bool||Active high reset signal, used to reset FIFOs and adc chip.|
|sdata||IN||UFix_8_0||Data to be written to the ADC registers over SPI. sdata[7:4] represents the register address, sdata[3:0] represents the new value to be written. Present only when SPI interface is enabled.|
|spi_strb||IN||Bool||SPI write strobe. When a positive edge is detected on this port an SPI write is initiated using the data and address presented on input sdata. Present only when SPI interface is enabled.|
|dout[0:15]||OUT||Fix_12_11||Four consecutive values of the signal represent a single time sample from four channels, with dout<n> representing channels 4n:4n+3.|
|chan_sync||OUT||UFix_8_0||A signal which goes high when a sample from channel 4n is present on output dout<n>. The 8 bits of the signal are used to sync the 8 individual ADC chips on the ADC card.|
The x64_adc block is an interface to the 64ADCx64-12 board developed by Rick Raffanti. The board is based around 8 Texas Instruments ADS5272 chips, each digitizing 8 signals at 12 bits resolution and up to 65MSa/s. The ADCs can be clocked by an on-board 50MHz oscillator, or an external clock source.
Connecting the ADC¶
The 64ADCx64-12 is a twin Z-DOK card. Only one can be connected to a ROACH board.
The x64_adc card includes an on-board 50MHz oscillator, but can also be driven by an external clock.
Header J4 controls selection of the ADC clock source. Leave J4 open to use the on-board 50MHz oscillator, or jumper J4 to use an external clock applied across resistor R9 via pins 36 and 38 of header J13.
The reset pin is located on pin 4 of J13. This signal is active low, and should be held high for normal operation. The yellow block interface is configured to drive the ADC reset pin via GPIO<A|B>_0, depending on the block parameter specified by the user. Note that the reset on the yellow block interface is active HIGH. When the ADC is held in reset, data output on the yellow block data lines will be the value -1 for all channels, in Fix_12_11 format.
- SCLK: pin 36, J12
- SDATA: pin 38, J12
- nCS: (ADC chip n): pin (20 + 2n), J12
- SCLK: GPIO<A|B>_2
- SDATA: GPIO<A|B>_1
- nCS: GPIO<A|B>_3
Where the GPIO port to use is determined by user-specified mask parameter. To write SPI registers, the “include SPI interface” option should be activated in the x64_adc yellow block parameters. This should expose the input ports “sdata” and “spi_strb” to the user. When a positive edge is detected on spi_strb, the data on sdata[3:0] is written to address sdata[7:4]. Currently, due to limited ROACH GPIO and lack of requirement, only one nCS signal is used by the yellow block. This can be connected to all ADC nCS pins, to write registers on all chips simultaneously.
The x64_adc block can take 64 analog input streams. The inputs are
Fix_12_11 numbers between [-1, 1).
The ADC card uses 8 separate chips, each providing its own clock over ZDOK to the FPGA. Rather than use all 8 clocks (some of which are not connected to clock enabled FPGA pins), a single clock is used, and the software calibration script File:X64 adc cal.txt is run to ensure that data from all ADC chips is properly aligned.
Note: There may be a problem while running this script as is. In case there is a problem While running the version available in the repository and throws the following error: unknown’x64_adc_ctrl’ variable, it can be fixed by adding the following line to the core_info.tab in the local repository (mlib_devel/blob/master/xps_base/XPS_ROACH_base/core_info.tab)
- IF# strcmp(get(b,’type’),’xps_x64_adc’)#x64_adc_ctrl 3 10000 100
Also, the following line of calibration script which is no longer supported by the ‘corr’ package can be removed (it seems this line was just meant for debugging).
fclk_sampled = self.bit_string((val0&0x0fff),12)
Data can be input for simulation using the sim<n> and sim_sync inputs. These inputs are passed straight to the dout<n> and chan_sync outputs, and should be controlled accordingly, taking into account the data output details above.