castro
- class castro.Castro(design_name, src_files, ips=[], mm_slaves=[], template_project=None)[source]
Stores complete generic structure design information
- class castro.ClkConstraint(portname, period_ns, freq_mhz=100, clkname=None, waveform_min_ns=None, waveform_max_ns=None, port_en=True, virtual_en=False)[source]
Class to hold a clock constraint
- class castro.ClkGrpConstraint(clknamegrp1=None, clknamegrp2=None, clkdomaintype=None)[source]
Class to hold a clock group constraint.
- class castro.FalsePthConstraint(sourcepath=None, destpath=None)[source]
Class to hold a false path constraint.
- class castro.GenClkConstraint(pinname, clkname=None, divide_by=None, clksource=None)[source]
Class to hold a generated clock constraint.
- class castro.InDelayConstraint(clkname=None, consttype=None, constdelay_ns=None, add_delay_en=None, portname=None)[source]
Class to hold an Input Delay constraint.
- class castro.MaxDelayConstraint(sourcepath=None, destpath=None, constdelay_ns=None)[source]
Class to hold a Max Delay constraint.
- class castro.MinDelayConstraint(sourcepath=None, destpath=None, constdelay_ns=None)[source]
Class to hold a Min Delay constraint.
- class castro.MultiCycConstraint(multicycletype=None, sourcepath=None, destpath=None, multicycledelay=None)[source]
Class to hold a multi cycle constraint.
- class castro.OutDelayConstraint(clkname=None, consttype=None, constdelay_ns=None, add_delay_en=None, portname=None)[source]
Class to hold an Output Delay constraint.
- class castro.PinConstraint(portname, symbolic_name, portname_indices=None, symbolic_indices=None, location='', drive_strength=None, slew_rate=0, io_standard='', diff_term=None)[source]
Class to hold a pin constraint
- class castro.RawConstraint(raw)[source]
Class to hold raw constraints. These are really against the spirit of castro, since they are tool-specific. But, being pragmatic, sometimes they are necessary to encode simple constraints, for highly technology-specific features. The contents of these is not defined by castro.
- class castro.Synthesis(platform_name='', fpga_manufacturer='', fpga_model='', synth_tool='', pin_map=[], vendor_constraints_files='', pin_constraints=[], clk_constraints=[], gen_clk_constraints=[], clk_grp_constraints=[], input_delay_constraints=[], output_delay_constraints=[], max_delay_constraints=[], min_delay_constraints=[], multi_cycle_constraints=[], false_path_constraints=[], raw_constraints=[], temp_fpga_model='', temp_quartus_qsf_files=[])[source]
A class to specify all the synthesis specific attributes of the design
- __init__(platform_name='', fpga_manufacturer='', fpga_model='', synth_tool='', pin_map=[], vendor_constraints_files='', pin_constraints=[], clk_constraints=[], gen_clk_constraints=[], clk_grp_constraints=[], input_delay_constraints=[], output_delay_constraints=[], max_delay_constraints=[], min_delay_constraints=[], multi_cycle_constraints=[], false_path_constraints=[], raw_constraints=[], temp_fpga_model='', temp_quartus_qsf_files=[])[source]