Real-sampled Wideband FFT¶
Computes the real-sampled Fast Fourier Transform using the standard Hermitian conjugation trick to use a complex core to transform a single real stream using half the normal resources (this requires at least 4 time samples in parallel). Only positive frequencies are output (negative frequencies are the mirror images of their positive counterparts), so there the number of output ports is half the number of input ports. Uses a biplex FFT architecture under the hood which has been extended to handle time samples in parallel. Data is output in normal frequency order, meaning that channel 0 (corresponding to DC) is output first, followed by channel 1, on up to channel 2N − 1 − 1.
|Number simultaneous streams
|The number of input data streams to be processed in parallel. Each stream consists of a set of parallel inputs set by another parameter (see Number of Simultaneous Inputs)
|Size of FFT: (2^?)
|The number of channels computed in the complex FFT core. The number of channels output for each real stream is half of this.
|Input Bit Width
|The number of bits in each real and imaginary sample as they are carried through the FFT. Each FFT stage will round numbers back down to this number of bits after performing a butterfly computation if bit growth is not enabled.
|To make optimal use of BRAM => 18 For low FFT noise => 25
|Input binary point
|The position of the binary point in the input data.
|Coefficient Bit Width
|The number of bits used in the real and imaginary part of the twiddle factors at each stage.
|Number of Simultaneous Inputs: (2^?)
|The number of parallel time samples which are presented to the FFT core each clock. This must be at least 22. The number of output ports is half of this value.
|Unscramble output (ie, put channels in canonical order)
|The FFT inherently produces data in an order that requires unscrambling before being used by many algorithms. This requires resources and can limit performance and so should be disabled if not necessary.
|Whether valid data is input on every clock cycle or is flagged via the en input port.
|Specifies the rounding behavior used at the end of each twiddle and butterfly computation to return to the number of bits specified above.
|Indicates the behavior of the FFT core when the value of a sample exceeds what can be expressed in the specified bit width.
|Wrap as Saturate will not make overflow corruption better behaved.
|Latency through adders in the FFT.
|Latency through multipliers in the FFT.
|Latency through BRAM in the FFT.
|2 For designs aimed at > 200MHz => 3
|Latency through blocks used to reduce bit widths after twiddle and butterfly stages.
|1 For designs aimed at > 180Mhz => 2
|Number bits above which to store stage’s coefficients in BRAM (2^? bits)
|Determines the threshold at which the twiddle coefficients in a stage are stored in BRAM. Below this threshold distributed RAM is used.
|8 (ensures at least 2^8=256 bits out of 18432 bits of BRAM used)
|Number bits above which to implement stage’s delays in BRAM (2^? bits)
|Determines the threshold at which data delays in a stage are stored in BRAM. Below this threshold distributed RAM is used.
|8 (ensures at least 2^8=256 bits out of 18432 bits of BRAM used)
|BRAM sharing in coeff storage
|Real and imaginary components of twiddle factors can be generated from the same set of coefficients, reducing BRAM use at the cost of some logic.
|Store a fraction of coeff factors where useful
|The full set of twiddle factors can be generated from a smaller set, reducing BRAM use at the cost of the some logic.
|Generate coeffs with multipliers where useful
|Generate twiddle factors in the internal fft_direct block using an oscillator with feedback.
|To reduce BRAM usage => on. To reduce multiplier usage => off
|Number calibration locations when generating coeffs (2^?)
|When generating twiddle factors with an oscillator with feedback, reference values are used to calibrate the complex exponential generated.
|For low BRAM usage => 1. For high quality twiddle factors => 9.
|Feedback rotation vector resolution
|When generating the twiddle factors, the resolution of the vector determines how much error accumulates.
|For low error => 25. For low BRAM usage => 18.
|The maximum fanout the twiddle factors are allowed to experience between where they are generated and when they are multiplied with the data stream. As the coefficients are shared, large fanout can occur which can affect maximum timing achievable. Decreasing the maximum fanout allowed should increase possible performance at the expense of some logic.
|Multiplier specification (0=core, 1=embedded, 2=behavioural) (left=1st stage)
|Array of values allowing exact specification of how multipliers are implemented at each stage.
|2 (behavioral HDL) for each stage
|Bit growth instead of shifting
|Bit growth at every stage in the FFT can result in overflows which affect data quality. This can be prevented by dividing the data by two on the output of every stage, or by increasing the number of bits in the data stream by one bit. Shifting decreases the dynamic range and possible data quality whereas bit growth increases the resource requirements.
|Max bits to growth to
|The maximum number of bits to increase the data path to when the bit growth option is chosen. Shifting is used for FFT stages after this.
|Hardcode shift schedule
|When shifting to prevent overflow, use a fixed shifting schedule. This uses less logic and increases performance when compared to using a dynamic shift schedule.
|When using a fixed shift schedule, use the shift schedule specified. A ‘1’ at position M in the array indicates a shift for the M’th FFT stage, a ‘0’ indicates no shift.
|DSP48 adders in butterfly
|The butterfly operation at each stage consists of two adders and two subtracters that can be implemented using DSP48 units instead of logic.
|on (enabled) to reduce logic used.
|sync is used to indicate the last data word of a frame of input data. When the block is in asynchronous operating mode an active signal is aligned with en being active. When the block is in synchronous operating mode, a an active pulse is aligned with the clock cycle before the first valid data of a new input frame.
|Ensure the sync period complies with the memo describing correct use.
|Sets the shifting schedule through the FFT to prevent overflow. Bit 0 specifies the behavior of stage 0, bit 1 of stage 1, and so on. If a stage is set to shift (with bit = 1), then every sample is divided by 2 at the output of that stage.
|Signed consisting of one (Input Bit Width) width signals per input.
|The time-domain stream(s) to be channelised.
|Data amplitude should not exceed 0.5 (divide data by 2 pre-FFT)
|When asynchronous operation is chosen, this port indicates that valid input data is available on all input data ports.
|Indicates that data out will be valid next clock cycle.
|The frequency channels.
|Unsigned, one bit per input stream
|Indication of internal arithmetic overflow. Not time aligned with data. The most significant bit is the flag for input stream 0 etc.
Computes the real-sampled Fast Fourier Transform using the standard Hermitian conjugation trick to use a complex core to transform a single real stream using half the normal resources (this requires at least 4 time samples in parallel). Only positive frequencies are output (negative frequencies are the mirror images of their positive counterparts), so there the number of output ports is half the number of input ports. Uses a biplex FFT architecture under the hood which has been extended to handled time samples in parallel. Data is output in normal frequency order, meaning that channel 0 (corresponding to DC) is output first, followed by channel 1, on up to channel 2N − 1 − 1.