CASPER X engine with added internal valid data masking functionality. Based on Aaron Parsons’ design.
|Number of antennas
|Number of antennas to process.
|Bit width of samples in
|Bit width of each input sample number. Usually set to 4, resulting in 16 bit input numbers (2 polarizations, complex numbers).
|Specified per antenna.
|Used to set the latency of internal adders.
|Used to set the latency of internal multipliers.
|Used to set the latency of internal BRAMs.
|Implementation: Multiplier type
|Select the type of multipliers to use. Can be a single number or array - see below.
|Implementation: Delay type
|Selects the type of delays to implement. Single number configures all internal taps.
|variable width. see below.
|Input port for incoming antenna data.
|Synchronization pulse. New window begins clock cycle after sync received.
|Indicates incoming antenna data is valid. Must remain constant for acc_len*n_ants.
|variable width. see below.
|Indicates data on acc is valid.
|Passthrough for sync pulses.
The CASPER X engine is a streaming architecture block where complex antenna data is input and accumulated products (for all cross-multiplications) are output in conjugated form. Because it is streaming with valid data expected on every clock cycle, data is logically divided into windows. These windows can either be valid (in which case the computation yields valid, outputted results) or invalid (in which case computation still occurs, but the results are ignored and not presented to the user).
Data is input serially:
antenna A, antenna B, antenna C etc. Each
antenna’s data consists of dual polarization, complex data. The bit
width of each component number can be set as a parameter,
The X-engine thus expects these four numbers of
n_bits to be
concatenated into a single, unsigned number. CASPER convention dictates
that complex numbers are represented with higher bits as real and lower
bits as imaginary. The top half of the input number is polarization one
and the lower half polarization two.
The internals of the block are reset with the reception of a sync pulse.
A new window begins on the very next clock cycle. Each window is
n_ants clock cycles long. The data for each
antenna is input for
acc_len clock cycles.
For example, for
n_bits of 4 and
acc_len of 2, the input to the
X-engine would be 16 bits every clock cycle mapped as follows:
X-engine input with
acc_len of 2.
window_valid line is expected to remain constant for the
duration of each window. If it is high, the output is considered valid
and captured into the output FIFO buffer. With the close of that window,
the output will be presented to the user as valid data on every second
clock pulse. If
window_valid was held low, the data is ignored.
With the close of one window, anther begins directly afterwards. Data can thus be streamed in and out continuously, while a sync pulse will force the start of a new window.
The windowed X-engine will produce valid outputs.
The unwindowed x engine produces results.
The extra valids are a result of the algorithm employed and are masked
out by the internal
Generally, the output of the X-engine configured for
N antennas can
be mapped into a table with columns and N
rows as follows:
Each table entry represents a valid output. Data is read out right to left, top to bottom. Bracketed values are from previous window.
As an example, consider the output for a 4 antenna system (with antennas numbered A through D):
|prev win DA
|prev win CA
|prev win BD
|next win AA
|next win BB
|next win AB
Boldfaced type represents current valid window of data. Data is read out right to left, top to bottom. Non-boldfaced data is masked.
Thanks to the inclusion of the
x_engine_mask block, X-engine output
duplicates (observed in rows 5 and 6 above) are automatically removed.
The output of a 4 antenna windowed X-engine is thus
AA, AB, BB, AC, BC, CC, BD, CD, DD, DA.