This block interfaces to the QDR SRAM devices on ROACH boards. Commands are executed at the rate they are applied, with synchronous and fixed timing. Data is always presented 10 cycles after a read is issued. Read and write data ports have 100% duty cycles.
|QDR Chip||which_qdr||Selects which physical QDR device to use (Two on ROACH V1).|
|Simulation QDR Address Width||qdr_awidth||Specifies the width of the address bus of the simulation model. (Limited to 18)|
|Use CPU Interface||use_cpu||Specify whether or not to include the QDR CPU interface, the removal of which may improve timing performance.|
|rd_en||in||boolean||Asserting this signal issues a read command. See below for details on issuing commands.|
|wr_en||in||boolean||Asserting this signal issues a write command. See below for details on issuing commands.|
|be||in||UFix_4||Selects bytes for writing (write byte enable). See below for behaviour relating to bursting and ECC bits.|
|address||in||UFix_32||Signal used as the QDR address. See below for behaviour relating to addressing.|
|wr_data||out||UFix_36||The data to written into the QDR. Bits 35:32 are ECC bits and are cleared when the processor writes to the corresponding byte. See below for behaviour relating to bursting and ECC bits.|
|data_valid||out||boolean||An active high signal indicating that the read data is valid.|
|ack||out||boolean||A signal indicating that the CPU interface is not accessing the memory.|
|phy_ready||out||boolean||A signal indicating that the QDR PHY has completed calibration, which takes very roughly 100us.|
|cal_fail||out||boolean||A signal indicating that the PHY calibration has failed.|
This document is a draft and requires verification.
There are two types of commands: reads and writes. They are issued by the rd_en and wr_en signals respectively. The QDR address is presented on the same cycle that the command is issues. One type of command cannot be issued in two consecutive cycles. When this happens, the second issue will be ignored. This is due to QDR supporting bursts to reduce data rates on the control signals. Further, if a read and write are issued at the same time the write will be ignored. However, if the previous command was a valid read, the current read will be ignored and the write will take preference.
When issuing reads and writes, data is presented on the respective data
ports for two cycles. When issuing a write command, the
be ports must be set for both the issuing cycle and the following
cycle. During a read response, data is issued on the same cycle that the
data_valid is asserted and on the following cycle.
The address presented when a command is issued addresses a full burst worth of memory i.e. 72 bits of data.
In hardware the QDR word is composed of four 9 bit components which are masked by the byte_enable signal. Each of these component include 8 data bits and a single ECC bit. This clashes with the byte-enable on the processor, which mask only 8 bits. For this reason the ECC bit gets cleared when the CPU writes to a byte of QDR memory. With this yellow block, the QDR data_in and data_out ports have the ECC bits on lines 35:32. This allows the four processor bytes to cleanly map to bits 31:0 of the data_in and data_out ports. This leads to a side-effect in the byte-enable behaviour as follows: be masks data_in bits [7:0] and , be mask data_in bits[15:8] and  etcetera.