yellow_blocks

adc

class yellow_blocks.adc.adc(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

adc16

class yellow_blocks.adc16.adc16(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

adc20g

class yellow_blocks.adc20g.adc20g(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

adc5g

class yellow_blocks.adc5g.adc5g(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

bram

class yellow_blocks.bram.bram(blk, platform, hdl_root=None)[source]
initialize()[source]

This function is called by YellowBlocks __init__ method. We could override __init__ here, but this seems a little bit more user friendly.

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

clock_passthrough

class yellow_blocks.clock_passthrough.clock_passthrough(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

dcp

class yellow_blocks.dcp.dcp(blk, platform, hdl_root=None)[source]
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

forty_gbe

class yellow_blocks.forty_gbe.forty_gbe(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

gpio

class yellow_blocks.gpio.gpio(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

gpio_bidir

class yellow_blocks.gpio_bidir.gpio_bidir(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

hmc

class yellow_blocks.hmc.hmc(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

instantiate_hmcc(top, num=None)[source]
modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

i2c_interface

class yellow_blocks.i2c_interface.i2c_interface(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by YellowBlocks __init__ method. We could override __init__ here, but this seems a little bit more user friendly.

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

ip

class yellow_blocks.ip.ip(blk, platform, hdl_root=None)[source]
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

lmx2581

class yellow_blocks.lmx2581.lmx2581(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

microblaze

class yellow_blocks.microblaze.microblaze(blk, platform, hdl_root=None)[source]
static factory(blk, plat, hdl_root=None)[source]
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

class yellow_blocks.microblaze.microblaze_k7(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.microblaze.microblaze_ku7(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

onegbe

class yellow_blocks.onegbe.onegbe(blk, platform, hdl_root=None)[source]
static factory(blk, plat, hdl_root=None)[source]
modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.onegbe.onegbe_casia_k7(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.onegbe.onegbe_skarab(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.onegbe.onegbe_snap(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.onegbe.onegbe_vcu118(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.onegbe.onegbe_vcu128(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

skarab

class yellow_blocks.skarab.skarab(blk, platform, hdl_root=None)[source]
gen_children()[source]

The toolflow will try to allow blocks to instantiate other blocks themselves, by calling this method. Override it in your subclass if you need to use this functionality.

Returns:A list of child YellowBlock instances
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

snap

class yellow_blocks.snap.snap(blk, platform, hdl_root=None)[source]
gen_children()[source]

The toolflow will try to allow blocks to instantiate other blocks themselves, by calling this method. Override it in your subclass if you need to use this functionality.

Returns:A list of child YellowBlock instances
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

snap2

class yellow_blocks.snap2.snap2(blk, platform, hdl_root=None)[source]
gen_children()[source]

The toolflow will try to allow blocks to instantiate other blocks themselves, by calling this method. Override it in your subclass if you need to use this functionality.

Returns:A list of child YellowBlock instances
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

snap_adc

class yellow_blocks.snap_adc.snap_adc(blk, platform, hdl_root=None)[source]
gen_children()[source]

The first instance of this adc adds the required clock controller module

gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
reorder_ports(port_list, wb_bitwidth=32)[source]

Reorder output ports of ADCs to arrange sampling data in correct order in wb_bram

wb_bitwidth stands for the bit width of data in/out port of wishbone bus

reorder_ports(['a1','a2','a3','a4'])
when self.adc_data_width == 8, return {a1,a2,a3,a4}
when self.adc_data_width == 16, return {a3,a4,a1,a2}
when self.adc_data_width == 32, return {a4,a3,a2,a1}

spi_wb_bridge

class yellow_blocks.spi_wb_bridge.spi_wb_bridge(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

sw_reg

class yellow_blocks.sw_reg.sw_reg(blk, platform, hdl_root=None)[source]
initialize()[source]

This function is called by YellowBlocks __init__ method. We could override __init__ here, but this seems a little bit more user friendly.

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

sw_reg_sync

class yellow_blocks.sw_reg_sync.sw_reg_sync(blk, platform, hdl_root=None)[source]
initialize()[source]

This function is called by YellowBlocks __init__ method. We could override __init__ here, but this seems a little bit more user friendly.

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

sys_block

class yellow_blocks.sys_block.sys_block(blk, platform, hdl_root=None)[source]
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

ten_gbe

class yellow_blocks.ten_gbe.ten_gbe(blk, platform, hdl_root=None)[source]
static factory(blk, plat, hdl_root=None)[source]
instantiate_ktge(top, num=None)[source]
class yellow_blocks.ten_gbe.tengbaser_xilinx_k7(blk, plat, hdl_root, use_gth=False)[source]
__init__(blk, plat, hdl_root, use_gth=False)[source]

Class constructor. Set up the initial values for block attributes, by copying key/val pairs from the blk dictionary. Call the class’s initialize() method, where the user should set compile parameters and override this class’s default attributes. Finally, call the class’s check_support() method, to verify that the block and platform chosen are compatible.

Parameters:
  • blk – A jasper-standard dictionary containing block information. Key/value pairs in this dictionary are copied to attributes of this instance.
  • platform – A Platform object representing the platform type.
  • hdl_root (Optional) – The path to a directory containing all hdl code necessary to instantiate this block. This root directory is used as a base from which block’s source files are defined. If None (default), will default to the system’s HDL_ROOT environment variable.
gen_children()[source]

The mx175 clocks the gth from a clock which is passed through the FPGA and through a jitter cleaner (si5324) back into the GTH clock port. The first ten gig core needs to make sure this pass through is instantiated.

gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

instantiate_infra(top, num)[source]
instantiate_phy(top, num)[source]
modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.ten_gbe.tengbaser_xilinx_ku7(blk, plat, hdl_root, use_gth=False)[source]
__init__(blk, plat, hdl_root, use_gth=False)[source]

Class constructor. Set up the initial values for block attributes, by copying key/val pairs from the blk dictionary. Call the class’s initialize() method, where the user should set compile parameters and override this class’s default attributes. Finally, call the class’s check_support() method, to verify that the block and platform chosen are compatible.

Parameters:
  • blk – A jasper-standard dictionary containing block information. Key/value pairs in this dictionary are copied to attributes of this instance.
  • platform – A Platform object representing the platform type.
  • hdl_root (Optional) – The path to a directory containing all hdl code necessary to instantiate this block. This root directory is used as a base from which block’s source files are defined. If None (default), will default to the system’s HDL_ROOT environment variable.
gen_children()[source]

The mx175 clocks the gth from a clock which is passed through the FPGA and through a jitter cleaner (si5324) back into the GTH clock port. The first ten gig core needs to make sure this pass through is instantiated.

gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

instantiate_infra(top, num)[source]
instantiate_phy(top, num)[source]
modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
class yellow_blocks.ten_gbe.tengbe_v2_xilinx_v6(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

vcu118

class yellow_blocks.vcu118.vcu118(blk, platform, hdl_root=None)[source]
gen_children()[source]

The toolflow will try to allow blocks to instantiate other blocks themselves, by calling this method. Override it in your subclass if you need to use this functionality.

Returns:A list of child YellowBlock instances
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

xadc

class yellow_blocks.xadc.xadc(blk, platform, hdl_root=None)[source]
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
initialize()[source]

This function is called by YellowBlocks __init__ method. We could override __init__ here, but this seems a little bit more user friendly.

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

xsg

class yellow_blocks.xsg.xsg(blk, platform, hdl_root=None)[source]

An xsg YellowBlock class, representing a CASPER “platform” block. I.e., the block which specifies which platform you are compiling for, and which clock (or other) compile-time settings you want to use.

Uses 2 attributes from the front end block configuration (in addition to the “platform” attribute which all YellowBlocks have access to): “clk_rate” (float): The clock rate, in MHz, the compile is targeting for the DSP pipeline. “clk_src” (string): The clock source (eg. “sys_clk”, “adc0_clk”, etc.) used to run the DSP pipeline.

This block is a little unlike other YellowBlocks – it has 3 jobs:

  1. Add a requirement – “self.requires.append(…)” – for a block in the design to provide – “self.provides.append(…)” – four clock phases:

    self.clk_src self.clk_src + “90” self.clk_src + “180” self.clk_src + “270”

    Probably, these clocks will be provided by the platform-specific block instantiated as a child of this block (see 3. below). Whichever block provides them must create signals with these names in the top-level verilog.

  2. Create wires in the top-level verilog desing, and assign the above clock signals to the new names: “user_clk” “user_clk90” “user_clk180” “user_clk270” This allows modules in the design to use these clock names, without requiring any knowledge about where they are coming from (eg. sys_clk, an ADC clock, etc). NOTE: Since this block instantiates clocks with these names, you MUST NOT use user_clkX signals elsewhere in your design.

  3. Instantiate a child YellowBlock, with identical parameters to this block, but with the class name self.platform.name. This is probably the instance you want to use to generate your custom clocks (eg, sys_clk, sys_clk90, …), so this block should add these signals to top-level verilog, and also “provide” them using the YellowBlock.provides mechanism.

gen_children()[source]

The toolflow will try to allow blocks to instantiate other blocks themselves, by calling this method. Override it in your subclass if you need to use this functionality.

Returns:A list of child YellowBlock instances
initialize()[source]

Things the toolflow has to know. eg, clocks needed/provided

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.

yellow_block

class yellow_blocks.yellow_block.YellowBlock(blk, platform, hdl_root=None)[source]

A yellow block object encodes all the information necessary to instantiate a piece of IP in an existing HDL base package.

  • which verilog modules need to be instantiated.
  • which instances need to be connected by signals
  • which ports of the instance need to be promoted to top-level
  • what is the type of these ports (for the constraints file)
  • is the device a slave on a CPU bus
  • if so, how much address space does it need?
  • what features does this block provide the rest of the system, e.g. clock sources
  • what fixed resources does this block use (e.g. QDR chip / ZDOK interface)

All the HDL related stuff is dealt with by the verilog module class, so we just need to add bus / memory space requirements and define what resources the block uses and provisions.

__init__(blk, platform, hdl_root=None)[source]

Class constructor. Set up the initial values for block attributes, by copying key/val pairs from the blk dictionary. Call the class’s initialize() method, where the user should set compile parameters and override this class’s default attributes. Finally, call the class’s check_support() method, to verify that the block and platform chosen are compatible.

Parameters:
  • blk – A jasper-standard dictionary containing block information. Key/value pairs in this dictionary are copied to attributes of this instance.
  • platform – A Platform object representing the platform type.
  • hdl_root (Optional) – The path to a directory containing all hdl code necessary to instantiate this block. This root directory is used as a base from which block’s source files are defined. If None (default), will default to the system’s HDL_ROOT environment variable.
add_build_dir_source()[source]

This function is neccessary as yellow blocks dont have access to the build directory when they want to add a source file that is not in hdl_lib this function can be used. Generate a list of dictionaries containing files/directories relative to the build_dir, which will be added to the sources of the project. to the project.

Eg.: []

{‘files’: ‘xml2vhdl_hdl_output/’, – this can be a directory or a file ‘library’ : ‘work’} – this is only used if the file needs to be included under a library (vhdl only) for verilog use ‘’

]

Returns:Dictionary of tcl command lists. Default {}
add_source(path)[source]

Add a source file to the list of files required to compile this yellow block. The path given should be relative to the root directory hdl_root. Globbing is supported.

Parameters:path – Path of file required for compilation. Eg “/some/source/file.v” or “/some/files*.v”
blk = None

Stores the blk parameter, passed into this block’s constructor.

check_support()[source]

Check the platform being used is supported by this block. Relies on subclasses to set the platform_support attribute appropriately in their initialize() methods. The default of the YellowBlock class is platform_support = 'all'.

Throw an error if the platform appears unsupported.

copy_attrs()[source]

Grab the dictionary entries of self.blk and turn them into attributes of this YellowBlock instance.

drc()[source]

Perform block-specific design rule checks. This method should be overridden by subclasses if any custom design checks are required.

exc_requires = None

“Exclusive requirements”. A list of strings, e.g. “zdok0”, “sfp2”, detailing a resources this block needs in order to compile. If another block tries to require the same resource, the compile will fail error checking.

gen_children()[source]

The toolflow will try to allow blocks to instantiate other blocks themselves, by calling this method. Override it in your subclass if you need to use this functionality.

Returns:A list of child YellowBlock instances
gen_constraints()[source]

Generate a list of Constraint objects, appropriate for this block. This method should be over-ridden by sub-classes to return a list of constraints as defined in constraints.py

Returns:A list of Constraint instances. Default is []
gen_custom_hdl()[source]

Generate a dictionary of custom hdl, to be saved as a file and added to the sources of the generated project. The key is the file name and the value is a string of HDL code to save in to that file. Eg.: {

‘my_hdl.vhdl’: [“<HDL code>”], ‘my_2nd_hdl.vhdl’ : [“<More HDL code>”],

}

Returns:Dictionary of hdl files. Default {}
gen_tcl_cmds()[source]

Generate a dictionary of tcl command lists, to be executed at compile time. Allowed keys are: init, pre_synth, synth, post_synth, pre_impl, impl, post_impl, pre_bitgen, bitgen, post_bitgen, prom_gem. The key used determines at what stage the tcl commands will be run.

Eg.:

{
    'pre_synth': ["first pre-synthesis tcl command", "second pre-synthesis tcl command"],
    'prom_gen' : ["A tcl command to generate a prom file after bit gen"],
}
Returns:Dictionary of tcl command lists. Default {}
hdl_root = None

The base directory from which source file’s locations are specified

i_am_the_first = None

A boolean, which is True if self.inst_id == 0

initialize()[source]

This function is called by the __init__() method. It is meant to be overridden by subclasses.

It should over-ride instance attributes to configure the block.

Common attributes which might be manipulated are: requires, exc_requires, provides, ips, sources, platform_supports

inst_id = None

The ID of this block within all the instances of this block’s class

ips = None

A list of IP dictionaries defining user-supplied IP to include with this block Dictionaries in this list have keys path (the path to the library) name (the name of the IP) module_name (the name of the HDL module this block defines) vendor, library, version (strings used by the backend to instantiate the IP)

logger = None

The jasper.yellowblock logger

static make_block(blk, platform, hdl_root=None)[source]

A builder function to return an instance of the correct YellowBlock subclass for a given type of block and target platform.

Parameters:
  • blk – A jasper-standard dictionary containing block information
  • platform – A Platform object representing the platform type.
Optional keyword param hdl_root:
 

The path to a directory containing all hdl code necessary to instantiate this block. This root directory is used as a base from which block’s source files are defined.

modify_top(top)[source]

Modify the VerilogModule instance top (so as to instantiate this module’s HDL) This method should be overridden by subclasses implementing their custom HDL requirements.

Parameters:top – A VerilogModule instance, defining the top-level of an HDL design into which this block should instantiate itself.
name = None

A friendly name for this block, generated from the tag entry in the self.blk dictionary and self.inst_id. Eg. “sw_reg5”, or “ten_gbe0”

platform = None

Stores the platform parameter, passed into this block’s constructor

platform_support = None

A list of platform names this block supports, or, the string “all”, indicating the block is platform agnostic.

provides = None

A list of strings, eg. “zdok0”, “sfp1”, detailing a resource this block provides to the design. These will me matched against self.requires and self.exc_requires of all the blocks in the design to determine if the compile is viable.

requires = None

A list of strings, eg. “zdok0”, “sfp1”, detailing a resource this block needs to compile. To pass rule-checking, every entry here must be matched with an entry in self.provides of another block, or the target platform

sources = None

A list of source files (paths relative to self.hdl_root) required by this module

throw_error(message)[source]

Raise an exception, showing the input message, but prefixing with a human-readable yellow block name.

typecode = None

A unique typecode indicating the type of yellow block this is. See yellow_block_typecodes.py. This code gets baked into a memory-map in the FPGA binary, and allows embedded software to figure out what type of devices are on the CPU bus.

yellow_block_typecodes

Here lie device typecode definitions. These codes get baked into toolflow-generate firmware can be used by embedded software to determine what types of devices are present on the CPU bus at different memory locations.

For example, a typical use case would be:

  1. MicroBlaze wakes up on programming a board
  2. Microblaze looks for an Ethernet core in the running firmware by searching for something in the firmware’s memory map with typecode TYPECODE_ETHCORE.
  3. MicroBlaze manipulates this device so as to talk to the outside world.

Values chosen are non-critical, but should be unique, and <256.