Programmable Fine Delay w/ Fringe stop, CORDIC¶
This block performs the fine delay correction along with the fringe stop. This block accepts the simultaneous stream of data from the FFT module and has a run time programmable fine delay correction along with the fringe stopping. This block uses CORDIC block which is compatible with Virtex 5 FPGA. Hence this block can be used for designs on Virtex5 FPGA of ROACH board.
Note 1: This block is specifically compatible with the “fft_wideband_real” module. For other FFT modules changes will be required in this block depending upon the way in which the data is output from the FFT module.
Note 2: This block requires System Generator Version 11.1 to make it compatible with Virtex 5.
Note 3: Currently the block is able to correct delay for One clock or less than one clock. It does not correct delays which are more than one clock.
|Number of simultaneous inputs||n_input||Number of simultaneous inputs (in frequency domain) from the FFT module.|
|Number of FFT channels||fft_len||Number of channels in the FFT|
|FFT input bitwidth||fft_bits||Number of bits in each real and imaginary samples obtained from the FFT module.|
|CORDIC Sine-Cos input bitwidth||theta_bits||Input bitwidth required for the CORDIC SineCos block and hence decides the resolution of the phase.|
|CORDIC Sine-Cos input binary bitwidth||theta_binary_bits||Input binary bitwidth of the CORDIC sine cos block.|
|Maximum number of FFT cycles (Rate of change of fringe = 2^?)||fft_cycle_bits||Number of FFT cycles after which the rate of change of fringe needs to be applied. The number of FFT cycles are specified in terms of powers of 2.|
|Sync Period||sync_period||Duration of the sync pulse.|
|sync||In||Boolean||Indicates the next clock cycle which contains valid data.|
|theta_fract||In||Unsigned||Sets the integer number required for fine delay correction.The bitwidth is equal to the address width for SineCos LUT. The method of calculating the range of integer required for the fine delay correction is explained in Description.|
|theta_fs||In||Unsigned||Sets the integer value equivalent to the initial phase value for fringe stop . The bitwidth is equal to the address width for SineCos LUT. Hence the possible range for initial phase varies from 0 to 2^theta_bits.|
|fft_fs||In||Unsigned||Sets the number of FFT cycles after which fringe update rate need to be applied.|
|en_theta_fs||In||Unsigned||This is the one bit control signal required to upload the new initial phase required for fringe stop. The new initial phase value gets loaded only at the posedge of this signal.|
|pol_in||In||Inherited||The frequency domain stream from the FFT module.|
|sync_out||Out||Boolean||Indicates that data out will be valid next clock cycle.|
|out||Out||Inherited||The fine delay and fringe stop corrected frequency channels.|
This block performs the fine delay correction along with the fringe stop. This block accepts the simultaneous stream of data from the FFT module and has a run time programmable fine delay correction along with the fringe stopping.This block uses CORDIC block which is compatible with Virtex 5 FPGA. Hence this block can be used for designs on Virtex5 FPGA of ROACH board.
Note: This block is specifically compatible with the “fft_wideband_real” module. For other FFT modules changes will be required in this block depending upon the way in which the data is output from the FFT module.
Fine Delay Correction:
Masking parameters like theta_bits and theta_binary_bits decides the resolution of the phase required for fine delay and fringe stop.
Resolution = (2^theta_bits * 2 * pi) / 8
For eg. theta_bits = 20 will generate a CORDIC SineCos block with a resolution of 0.000437 degrees.
Let bandwidth = 300MHz and no. of FFT channels = fft_len = 1024 then the maximum integer value of theta_fract (i.e. max fine delay = 1 clk cycle)will be
num = (2^theta_bits * pi) / 8
x = (num * 2)/(fft_len/2) = 1608
Thus 1/1608th of the clock cycle delay can be compensated with the above parameters.
Masking parameter fft_cycle_bits determines the maximum number of FFT cycles after which the fringe phase will be incremented.
For eg. Let the sync period is of 2^27 clks and number of FFT points be 2^10 then the maximum number of FFT cycles for incrementing the fringe phase by amount of resolution set for the Sine-Cos LUT = 2^27 / 2^10 = 2^17
It means that minimum rate of incrementing fringe phase by 0.000437 degrees is after 2^17 FFT cycles.