The sram block represents a 36x512k SRAM chip on the IBOB. It stores 36-bit words and requires 19 bits to access its address space.
|Selects which SRAM chip this block represents.
|Type to which the data is cast on both the input and output.
|Data binary point (bitwidth is 36)
|Position of the binary point of the data.
|Sets the period with reference to the clock frequency.
|Simulate SRAM using ModelSim
|Turns ModelSim simulation on or off.
|A signal that when high, causes the data on data_in to be written to address.
|A signal that enables different 9-bit bytes of data_in to be written.
|A signal that specifies the address where either data_in is to be stored or from where data_out is to be read.
|A signal that contains the data to be stored.
|A signal that contains the data coming out of address.
|A signal that is high when data_out is valid.
The SRAM block is 36x512k, signifying that its input and output are
36-bit words and it can store 512k words. Each clock cyle, if
high, then each bit of be determines whether each 9-bit chunk will be
written to address.
be is 4 bits with the highest bit corresponding
to the most significant chunk (so if
be is 1100, only the top 18
bits will be written). If
we is low, then the SRAM block ignores
data_in and be and reads the word stored at