constraints

class constraints.ClockConstraint(signal=None, name=None, freq=None, period=None, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=None)[source]

A clock constraint – simply holds the name of the clock signal, clock name, whether clock source is get_ports or get_pins, whether a virtual clock, waveform parameters for duty cycle and the corresponding clock freq and period.

This assigns the clock timing constraint on the clock port in user_const.xdc, for example:

ClockConstraint('A','A', period=6.4, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=3.2)) is translated to create_clock -period 6.400 -name A -waveform {0.000 3.200} [get_ports {A}] in the xdc file.

This tells Vivado which ports should be clocks.

__init__(signal=None, name=None, freq=None, period=None, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=None)[source]

Construct a ClockConstraint instance.

Parameters:
  • signal (str) – The signal name of the clock port
  • name (str) – The name of the clock
  • freq (float) – The clock frequency in MHz (no need to specify period if the frequency is specified)
  • period (float) – The period of the clock in ns (no need to specify frequency if the period is specified)
  • port_en (boolean) – If True then the clock port is enabled. If False then the clock port is bypassed for the case of a virtual clock.
  • virtual_en (bool) – This is set to True when using a virtual clock, otherwise it is False.
  • waveform_min (float) – This parameter is used to determine the duty cycle of the clock in ns. Typically 0ns.
  • waveform_max (float) – This parameter is used to determine the duty cycle of the clock in ns. Typically half the period of the clock for a 50% duty cycle.
class constraints.ClockGroupConstraint(clock_name_group_1=None, clock_name_group_2=None, clock_domain_relationship=None)[source]

A clock group constraint – simply holds the name of both clock domains and the domain relationship e.g. asynchronous

This assigns the clock group timing constraint on two or more clock groups in user_const.xdc, for example:

ClockGroupConstraint('A', 'B', 'asynchronous') is translated to set_clock_groups -asynchronous -group [get_clocks A] -group [get_clocks B] in the xdc file.

This constraint is used to cut the clock relationship between two or more clock groups.

__init__(clock_name_group_1=None, clock_name_group_2=None, clock_domain_relationship=None)[source]

Construct a ClockGroupConstraint instance.

Parameters:
  • clock_name_group_1 (str) – The clock name of the first group e.g. the clock port name or virtual clock name
  • clock_name_group_2 (str) – The clock name of the second group e.g. the clock port name or virtual clock name
  • clock_domain_relationship (str) – This specifies the relationship between the two clock name groups. Typically this is set to asynchronous which tells the Vivado timing analyzer to ignore the timing relationship between these two clock domains, as the clocks are asynchronous.
class constraints.FalsePathConstraint(sourcepath=None, destpath=None)[source]

A false path constraint - simply holds the source and destination paths.

This assigns the false path timing constraint in user_const.xdc, for example:

FalsePathConstraint(destpath='[get_ports {A}]') is translated to set_false_path -to [get_ports {A}] in the xdc file.

Any path that appears in the FalsePathConstraint is ignored by the Vivado timing analyzer.

__init__(sourcepath=None, destpath=None)[source]

Construct a FalsePathConstraint instance.

Parameters:
  • sourcepath (str) – The source path that the constraint is applied to - includes path and port names.
  • destpath (str) – The destination path that the constraint is applied to - includes path and port names.
class constraints.GenClockConstraint(signal, name=None, divide_by=None, clock_source=None)[source]

A clock generation constraint – simply holds the name of the clock signal, clock name, clock source and divide by value.

This assigns the generated clock timing constraint on a non global clock port in user_const.xdc, for example:

GenClockConstraint(signal='sub/Q', name='sub/CLK', divide_by=16, clock_source='sub/C') is translated to create_generated_clock -name sub/CLK -source [get_pins {sub/C}] -divide_by 16 [get_pins {sub/Q}] in the xdc file.

This constraint is used to assign a clock to signals that are not inferred by Vivado naturally and should be.

__init__(signal, name=None, divide_by=None, clock_source=None)[source]

Construct a GenClockConstraint instance.

Parameters:
  • signal (str) – The signal name that is required to be a clock
  • name (str) – The name of the generated clock
  • divide_by (int) – The value to divide the clock_source by in order to determine the clock frequency of the generated clock in MHz
  • clock_source (str) – This is the clock source (input) of the generated clock. The clock_source and the divide_by value determined the generated clock out frequency in MHz: generated clock in MHz = clock_source*divide_by
class constraints.InputDelayConstraint(clkname=None, consttype=None, constdelay_ns=None, add_delay_en=None, portname=None)[source]

An input delay constraint - simply holds the name of the reference clock, constraint type (min or max), constraint delay value (ns), whether an existing constraint exists and a new one needs to be added and the port name that the constraint applies to.

This assigns the clock input delay timing constraint in user_const.xdc, for example: InputDelayConstraint(clkname='A', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='B') is translated to set_input_delay -clock [get_clocks A] -min -add_delay 1.000 [get_ports {B}] in the xdc file.

This constraint is used to assign input constraints referenced to the clock.

__init__(clkname=None, consttype=None, constdelay_ns=None, add_delay_en=None, portname=None)[source]

Construct a InputDelayConstraint instance.

Parameters:
  • clkname (str) – The clock name which the port name is referenced to
  • consttype (str) – This is constraint type: either be a min (hold) or max (setup).
  • constdelay_ns (float) – This is the constraint delay in ns - takes into account the Tco, clock skew and board delay.
  • add_delay_en (bool) – If more than one constraint is needed on the portname then this is True, else set it to False.
  • portname (str) – The port name of the signal that needs to be constrained.
class constraints.MaxDelayConstraint(sourcepath=None, destpath=None, constdelay_ns=None)[source]

A set max delay constraint - simply holds the source, destination paths and the constraint delay value (ns).

This assigns the max delay timing constraint in user_const.xdc, for example: MaxDelayConstraint(destpath='[get_ports {A}]', constdelay_ns=1.0) is translated to set_max_delay 1.0 -to [get_ports {A}] in the xdc file.

This constraint is used when there is no clock reference.

__init__(sourcepath=None, destpath=None, constdelay_ns=None)[source]

Construct a MaxDelayConstraint instance.

Parameters:
  • sourcepath (str) – The source path that the constraint is applied to - includes path and port names.
  • destpath (str) – The destination path that the constraint is applied to - includes path and port names.
  • constdelay_ns (float) – This is the constraint delay in ns - takes into account the Tsu, clock skew and board delay.
class constraints.MinDelayConstraint(sourcepath=None, destpath=None, constdelay_ns=None)[source]

A set min delay constraint - simply holds the source, destination paths and the constraint delay value (ns).

This assigns the min delay timing constraint in user_const.xdc, for example:

MinDelayConstraint(destpath='[get_ports {A}]', constdelay_ns=1.0) is translated to set_min_delay 1.0 -to [get_ports {A}] in the xdc file.

This constraint is used when there is no clock reference.

__init__(sourcepath=None, destpath=None, constdelay_ns=None)[source]

Construct a MinDelayConstraint instance.

Parameters:
  • sourcepath (str) – The source path that the constraint is applied to - includes path and port names.
  • destpath (str) – The destination path that the constraint is applied to - includes path and port names.
  • constdelay_ns (float) – This is the constraint delay in ns - takes into account the Th, clock skew and board delay.
class constraints.MultiCycleConstraint(multicycletype=None, sourcepath=None, destpath=None, multicycledelay=None)[source]

A multi cycle constraint - simply holds the multi cycle type (steup or hold), source, destination paths and multi cycle delay value in clock cycles.

This assigns the multicycle timing constraint in user_const.xdc, for example:

MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks B', destpath='get_ports A', multicycledelay=4) is translated to set_multicycle_path -setup -from [get_ports A] -to [get_clocks B] 4 in the xdc file.

This tells the Vivado timing analyzer that the signal will take more than one clock cycle to propagate through the logic.

__init__(multicycletype=None, sourcepath=None, destpath=None, multicycledelay=None)[source]

Construct a MultiCycleConstraint instance.

Parameters:
  • multicycletype (str) – The type of multicycle constraint: either setup or hold
  • sourcepath (str) – The source path that the constraint is applied to - includes path and port names.
  • destpath (str) – The destination path that the constraint is applied to - includes path and port names.
  • multicycledelay (int) – This represents the number of clock cycles to delay.
class constraints.OutputDelayConstraint(clkname=None, consttype=None, constdelay_ns=None, add_delay_en=None, portname=None)[source]

An output delay constraint - simply holds the name of the reference clock, constraint type (min or max), constraint delay value (ns), whether an existing constraint exists and a new one needs to be added and the port name that the constraint applies to.

This assigns the clock output delay timing constraint in user_const.xdc, for example:

OutputDelayConstraint(clkname='A', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='B') is translated to set_output_delay -clock [get_clocks A] -min -add_delay 1.000 [get_ports {B}] in the xdc file.

This constraint is used to assign output constraints referenced to the clock.

__init__(clkname=None, consttype=None, constdelay_ns=None, add_delay_en=None, portname=None)[source]

Construct a OutputDelayConstraint instance.

Parameters:
  • clkname (str) – The clock name which the port name is referenced to
  • consttype (str) – This is constraint type: either be a min (hold) or max (setup).
  • constdelay_ns (float) – This is the constraint delay in ns - takes into account the Tsu, Th, clock skew and board delay.
  • add_delay_en (bool) – If more than one constraint is needed on the portname then this is True, else set it to False.
  • portname (str) – The port name of the signal that needs to be constrained.
class constraints.PortConstraint(portname, iogroup, port_index=[], iogroup_index=[0], loc=None, iostd=None, drive_strength=None, diff_term=None)[source]

A class to facilitate constructing abstracted port constraints.

Eg, adc_data[7:0] <=> zdok0[7:0] which can later be translated into physical constraints by providing information about a target platform.

This assigns the port LOC and voltage constraints to user_const.xdc, for example:

PortConstraint('A', 'A') is translated to set_property PACKAGE_PIN BC27 [get_ports A] and set_property IOSTANDARD LVCMOS18 [A] in the xdc file. The “BC27” LOC and “LVCMOS18” is determined by the platform yaml file, which contains all the platform top level ports and LOC assignments.

__init__(portname, iogroup, port_index=[], iogroup_index=[0], loc=None, iostd=None, drive_strength=None, diff_term=None)[source]

Construct a PortConstraint instance.

Parameters:
  • portname (str) – The name (in verilog) of the port
  • port_index (int) – Specify an offset of the port index to attach to iogroup[index]. This feature was added so that we can do (eg.) myport[3:0] <=> gpioA[3:0], myport[7:4] <=> gpioB[3:0]
  • iogroup (str) – The abstract name of the ports physical connection (eg. zdok0, zdok1, gpioa)
  • iogroup_index (int or list) – The index of the abstract name to which the HDL port should connect
  • loc (list of ints) – Specify a loc to construct a physical constraint, forgoing the abstract names. Experimental.
  • iostd – Specify an iostd to construct a physical constraint, forgoing the abstract names. Experimental.
  • drive_strength – Specify a drive strength to construct a physical constraint, forgoing the abstract names. Experimental.
  • diff_term (list of str) – specify the use of internal 100 ohm termination for lvds pins. set to TERM_100 or TERM_NONE (default). Experimental.
gen_physical_const(platform)[source]

Set the LOC and IOSTDs of an abstract constraint for a given platform.

Parameters:platform (Platform) – The platform instance against which to evaluate the constraint(s).
class constraints.RawConstraint(const)[source]

A class for raw constraints – strings to be dumper unadulterated into a constraint file.

This assigns any raw constraints (set_property, pblock etc) in user_const.xdc, for example:

RawConstraint('set_property OFFCHIP_TERM NONE [get_ports A]') is translated to set_property OFFCHIP_TERM NONE [get_ports A] in the xdc file.

Any constraint not handled in the above classes can be added using the raw constraints.

__init__(const)[source]

Construct a RawConstraint instance.

Parameters:const (str) – This represents the path with port names that the constraint is applied to