Welcome to the documentation for
mlib_devel, the CASPER Toolflow!
What is mlib_devel?¶
mlib_devel repository contains a set of FPGA DSP libraries and programming tools developed and maintained by the Collaboration for Astronomical Signal Processing and Electronics Research (CASPER). Within the collaboration, this collection of software is affectionately referred to as The Toolflow.
The CASPER toolflow allows you to generate signal processing designs using MATLAB’s graphical programming tool
Simulink. These designs can be turned into FPGA bitstreams and loaded onto a variety of supported hardware platforms to perform real-time digital signal processing systems. CASPER also provides a Python software library for interacting with running designs: casperfpga.
For more information about installing and using the CASPER Toolflow, see the project’s documentation.
CASPER also maintain a set of tutorials, designed to introduce new users to the toolflow.
Updating an Existing Toolflow Installation¶
You can always update your installation of mlib_devel by pulling updated code from this repository. If you do this, chances are you’ll need to update your Simulink models to match your new mlib_devel libraries. A script is provided to automate this process. With your model open and active, in your MATLAB prompt, run
This script will resynchronize every CASPER block in your design with its latest library version. Depending on the size of your model, it may take many minutes to complete! As always, back up your designs before attempting such a major operation. And, if you experience problems, please raise Github issues!
mlib_devel directory structure¶
- Simulink DSP libraries
- Simulink libraries for tool-flow supported modules (ADC interfaces, Ethernet cores, etc.)
- HDL code and Xilinx EDK wrappers used in older (ROACH2 and earlier) versions of the toolflow.
- Sphinx documentation for the software in this project.
Python and MATLAB scripts required to drive the compilation process. Also platform-dependent configuration information and source-code for IP modules used by the toolflow in the following directories.
- YAML files defining the compile parameters and physical constraints of CASPER-supported FPGA platforms.
- Golden boot images for FPGA platforms which require them.
- HDL source files for all toolflow-suppled modules (eg. ADC interfaces, Ethernet cores, etc.).
- Codebase for embedded software processors used by the toolflow
- Python classes for each yellow block in the simulink xps_library.
The software stack you will require to use the toolflow will depend what hardware you are targeting. Older hardware (ROACH2 and earlier) use the older Xilinx software (ISE) which forces the use of different tools.
The current compatibility matrix is below:
|Hardware||Operating System||Matlab Version||Xilinx Version||mlib_devel branch / commit||Python Version|
|ROACH1/2||Ubuntu 14.04||2013b||ISE 14.7||branch: roach||Python 2.7|
|SKARAB||Ubuntu 16.04||2018a||Vivado 2019.1.1||branch: master||Python 3|
|SNAP||Ubuntu 16.04||2018a||Vivado 2019.1.1||branch: master||Python 3|
|Red Pitaya||Ubuntu 16.04||2018a||Vivado 2019.1.1||branch: master||Python 3|
|VCU118||Ubuntu 16.04||2018a||Vivado 2019.1.1||branch: master||Python 3|
|VCU128||Ubuntu 16.04||2018a||Vivado 2019.1.1||branch: master||Python 3|
|ZCU111||Ubuntu 16.04||2018a||Vivado 2019.1.1||branch: master||Python 3|
|SNAP2||Ubuntu 16.04||2016b||Vivado 2016.4||branch: master||Python 3|
The recommended OS is Ubuntu as it is what the majority of the collaboration are using. This makes it easier for us to support you. If you are so inclined, you could also use Red Hat, but we definitely do not support Windows. You are welcome to try but you will be on your own. You could always run Linux in a VM although this will increase your compile times.
Please refer to the setup links below for more information on setting up the toolflow.
- CASPER Tutorials
- AXI Documentation
- Block Documentation
- Toolflow Documentation
- Toolflow Sourcecode
- casperfpga Sourcecode