Source code for yellow_blocks.skarab

import os
from .yellow_block import YellowBlock
from constraints import PortConstraint, ClockConstraint, GenClockConstraint, ClockGroupConstraint, InputDelayConstraint,\
    OutputDelayConstraint, MaxDelayConstraint, MinDelayConstraint, FalsePathConstraint, MultiCycleConstraint, RawConstraint
from clk_factors import clk_factors


[docs]class skarab(YellowBlock):
[docs] def initialize(self): self.add_source('skarab_infr/skarab_parameters.vhd/') self.add_source('skarab_infr/skarab_infr.vhd') self.add_source('wbs_arbiter/*.v') self.add_source('wbs_arbiter/timeout.v') self.add_source('wishbone_i2c') self.add_source('wishbone_one_wire') self.add_source('skarab_infr/WISHBONE') self.add_source("skarab_infr/cont_microblaze/cont_microblaze.bd") self.add_source("skarab_infr/cont_microblaze/hdl/cont_microblaze_wrapper.vhd") self.add_source("skarab_infr/cont_microblaze/EMB123701U1R1.elf") self.add_source("skarab_infr/xadc_measurement/*.xci") self.add_source('skarab_infr/*.v') self.add_source('skarab_infr/*.vhd') self.add_source('skarab_infr/*.sv') self.add_source("skarab_infr/cross_clock_fifo_36x16/*.xci") self.add_source("skarab_infr/cross_clock_fifo_wb_out_73x16/*.xci") self.add_source("skarab_infr/common_clock_fifo_32x16/*.xci") self.add_source("forty_gbe/ska_cpu_buffer/*.xci") self.add_source("forty_gbe/arp_cache/*.xci") self.add_source("forty_gbe/arp_cache/arp_cache.coe") self.add_source("skarab_infr/isp_spi_buffer/*.xci")
[docs] def modify_top(self,top): #multiply, divide, divclk = clk_factors(156.25, self.platform.user_clk_rate) self.clkparams = clk_factors(156.25, self.platform.user_clk_rate) self.fullname = 'skarab_infr' #inst = top.get_instance(name=self.fullname, entity='skarab_infr') inst = top.get_instance(name='skarab_infr', entity='skarab_infr') self.fullname = 'skarab_infr' # mmcm specific parameters inst.add_parameter('MULTIPLY', self.clkparams[0]) inst.add_parameter('DIVIDE', self.clkparams[1]) inst.add_parameter('DIVCLK', self.clkparams[2]) inst.add_port('user_clk_o', 'sys_clk', dir='out') inst.add_port('user_rst_o', 'sys_rst', dir='out') inst.add_port('hmc_clk_o', 'hmc_clk', dir='out') inst.add_port('hmc_rst_o', 'hmc_rst', dir='out') inst.add_port('board_clk_o', 'board_clk', dir='out') inst.add_port('board_clk_rst_o', 'board_clk_rst', dir='out') inst.add_port('qsfp_gtrefclk', 'qsfp_gtrefclk_0', dir='in', parent_sig=False) # only the first 40gbe core drives this ref clk inst.add_port('qsfp_soft_reset_0', 'qsfp_soft_reset_0', dir='out') inst.add_port('qsfp_soft_reset_1', 'qsfp_soft_reset_1', dir='out') inst.add_port('qsfp_soft_reset_2', 'qsfp_soft_reset_2', dir='out') inst.add_port('qsfp_soft_reset_3', 'qsfp_soft_reset_3', dir='out') inst.add_port('GND', 'GND', parent_port=True, dir='out', width=16) inst.add_port('gbe_phy_up' , 'gbe_link_up' , parent_sig=True, dir='in') inst.add_port('fgbe_phy_rx_up_0', 'fgbe_phy_rx_up_0', parent_sig=True, dir='in') inst.add_port('fgbe_phy_rx_up_1', 'fgbe_phy_rx_up_1', parent_sig=True, dir='in') inst.add_port('fgbe_phy_rx_up_2', 'fgbe_phy_rx_up_2', parent_sig=True, dir='in') inst.add_port('fgbe_phy_rx_up_3', 'fgbe_phy_rx_up_3', parent_sig=True, dir='in') inst.add_port('gbe_status_vector' , 'gbe_status_vector' , parent_sig=True, dir='in') inst.add_port('gmii_clk', 'gmii_clk' , parent_sig=True, dir='in') inst.add_port('gmii_reset_done', 'gmii_reset_done' , parent_sig=True, dir='in') inst.add_port('sync_gmii_fpga_rst_o', 'sync_gmii_fpga_rst', parent_sig=True, dir='out') inst.add_port('gbe_if_present', 'gbe_if_present', parent_sig=True, dir='in') inst.add_port('fgbe_if_0_present', 'fgbe_if_0_present', parent_sig=True, dir='in') inst.add_port('fgbe_if_1_present', 'fgbe_if_1_present', parent_sig=True, dir='in') inst.add_port('fgbe_if_2_present', 'fgbe_if_2_present', parent_sig=True, dir='in') inst.add_port('fgbe_if_3_present', 'fgbe_if_3_present', parent_sig=True, dir='in') inst.add_port('xlgmii_txled_0', 'xlgmii_txled_0', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_rxled_0', 'xlgmii_rxled_0', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_txled_1', 'xlgmii_txled_1', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_rxled_1', 'xlgmii_rxled_1', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_txled_2', 'xlgmii_txled_2', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_rxled_2', 'xlgmii_rxled_2', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_txled_3', 'xlgmii_txled_3', width=2, parent_sig=True, dir='in') inst.add_port('xlgmii_rxled_3', 'xlgmii_rxled_3', width=2, parent_sig=True, dir='in') inst.add_port('FPGA_RESET_N', 'FPGA_RESET_N', parent_port=True, dir='in') inst.add_port('FPGA_REFCLK_BUF0_P', 'FPGA_REFCLK_BUF0_P', parent_port=True, dir='in') inst.add_port('FPGA_REFCLK_BUF0_N', 'FPGA_REFCLK_BUF0_N', parent_port=True, dir='in') inst.add_port('FPGA_REFCLK_BUF1_P', 'FPGA_REFCLK_BUF1_P', parent_port=True, dir='in') inst.add_port('FPGA_REFCLK_BUF1_N', 'FPGA_REFCLK_BUF1_N', parent_port=True, dir='in') inst.add_port('MEZZ0_SDA_IN', 'mez0_sda_out', dir='in') inst.add_port('MEZZ0_SDA_OUT', 'mez0_sda_in', dir='out') inst.add_port('MEZZ0_SCL_IN', 'mez0_scl_out', dir='in') inst.add_port('MEZZ0_SCL_OUT', 'mez0_scl_in', dir='out') inst.add_port('MEZZ0_INIT_DONE', 'mez0_init_done', dir='in') inst.add_port('MEZZ0_POST_OK', 'mez0_post_ok', dir='in') inst.add_port('MEZZ0_ID', 'mez0_id', dir='in', width=3) inst.add_port('MEZZ0_PRESENT', 'mez0_present', dir='in') inst.add_port('MEZZ1_SDA_IN', 'mez1_sda_out', dir='in') inst.add_port('MEZZ1_SDA_OUT', 'mez1_sda_in', dir='out') inst.add_port('MEZZ1_SCL_IN', 'mez1_scl_out', dir='in') inst.add_port('MEZZ1_SCL_OUT', 'mez1_scl_in', dir='out') inst.add_port('MEZZ1_INIT_DONE', 'mez1_init_done', dir='in') inst.add_port('MEZZ1_POST_OK', 'mez1_post_ok', dir='in') inst.add_port('MEZZ1_ID', 'mez1_id', dir='in', width=3) inst.add_port('MEZZ1_PRESENT', 'mez1_present', dir='in') inst.add_port('MEZZ2_SDA_IN', 'mez2_sda_out', dir='in') inst.add_port('MEZZ2_SDA_OUT', 'mez2_sda_in', dir='out') inst.add_port('MEZZ2_SCL_IN', 'mez2_scl_out', dir='in') inst.add_port('MEZZ2_SCL_OUT', 'mez2_scl_in', dir='out') inst.add_port('MEZZ2_INIT_DONE', 'mez2_init_done', dir='in') inst.add_port('MEZZ2_POST_OK', 'mez2_post_ok', dir='in') inst.add_port('MEZZ2_ID', 'mez2_id', dir='in', width=3) inst.add_port('MEZZ2_PRESENT', 'mez2_present', dir='in') inst.add_port('MEZZANINE_0_PRESENT_N', 'MEZZANINE_0_PRESENT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_0_ENABLE_N', 'MEZZANINE_0_ENABLE_N', parent_port=True, dir='out') # inst.add_port('MEZZANINE_0_RESET', 'MEZZANINE_0_RESET', parent_port=True, dir='out') inst.add_port('MEZZANINE_0_FAULT_N', 'MEZZANINE_0_FAULT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_0_ONE_WIRE', 'MEZZANINE_0_ONE_WIRE', parent_port=True, dir='inout') # inst.add_port('MEZZANINE_0_CLK_SEL', 'MEZZANINE_0_CLK_SEL', parent_port=True, dir='out') inst.add_port('MEZZANINE_0_SCL_FPGA', 'MEZZANINE_0_SCL_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_0_SDA_FPGA', 'MEZZANINE_0_SDA_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_0_INT_N', 'MEZZANINE_0_INT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N', 'MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N', parent_port=True, dir='out') inst.add_port('MEZZANINE_1_PRESENT_N', 'MEZZANINE_1_PRESENT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_1_ENABLE_N', 'MEZZANINE_1_ENABLE_N', parent_port=True, dir='out') # inst.add_port('MEZZANINE_1_RESET', 'MEZZANINE_1_RESET', parent_port=True, dir='out') inst.add_port('MEZZANINE_1_FAULT_N', 'MEZZANINE_1_FAULT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_1_ONE_WIRE', 'MEZZANINE_1_ONE_WIRE', parent_port=True, dir='inout') # inst.add_port('MEZZANINE_1_CLK_SEL', 'MEZZANINE_1_CLK_SEL', parent_port=True, dir='out') inst.add_port('MEZZANINE_1_SCL_FPGA', 'MEZZANINE_1_SCL_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_1_SDA_FPGA', 'MEZZANINE_1_SDA_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_1_INT_N', 'MEZZANINE_1_INT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N', 'MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N', parent_port=True, dir='out') inst.add_port('MEZZANINE_2_PRESENT_N', 'MEZZANINE_2_PRESENT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_2_ENABLE_N', 'MEZZANINE_2_ENABLE_N', parent_port=True, dir='out') # inst.add_port('MEZZANINE_2_RESET', 'MEZZANINE_2_RESET', parent_port=True, dir='out') inst.add_port('MEZZANINE_2_FAULT_N', 'MEZZANINE_2_FAULT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_2_ONE_WIRE', 'MEZZANINE_2_ONE_WIRE', parent_port=True, dir='inout') # inst.add_port('MEZZANINE_2_CLK_SEL', 'MEZZANINE_2_CLK_SEL', parent_port=True, dir='out') inst.add_port('MEZZANINE_2_SCL_FPGA', 'MEZZANINE_2_SCL_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_2_SDA_FPGA', 'MEZZANINE_2_SDA_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_2_INT_N', 'MEZZANINE_2_INT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N', 'MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N', parent_port=True, dir='out') inst.add_port('MEZZANINE_3_PRESENT_N', 'MEZZANINE_3_PRESENT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_3_ENABLE_N', 'MEZZANINE_3_ENABLE_N', parent_port=True, dir='out') inst.add_port('MEZZANINE_3_RESET', 'MEZZANINE_3_RESET', parent_port=True, dir='out') inst.add_port('MEZZANINE_3_FAULT_N', 'MEZZANINE_3_FAULT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_3_ONE_WIRE', 'MEZZANINE_3_ONE_WIRE', parent_port=True, dir='inout') inst.add_port('MEZZANINE_3_CLK_SEL', 'MEZZANINE_3_CLK_SEL', parent_port=True, dir='out') inst.add_port('MEZZANINE_3_SCL_FPGA', 'MEZZANINE_3_SCL_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_3_SDA_FPGA', 'MEZZANINE_3_SDA_FPGA', parent_port=True, dir='inout') inst.add_port('MEZZANINE_3_INT_N', 'MEZZANINE_3_INT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N', 'MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N', parent_port=True, dir='out') inst.add_port('ONE_GBE_LINK', 'ONE_GBE_LINK', parent_port=True, dir='in') inst.add_port('GBE_INT_N', 'ONE_GBE_INT_N', parent_sig=True, parent_port=True, dir='in') inst.add_port('ONE_WIRE_EEPROM', 'ONE_WIRE_EEPROM', parent_port=True, dir='inout') inst.add_port('ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N', 'ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N', parent_port=True, dir='out') inst.add_port('I2C_SCL_FPGA', 'I2C_SCL_FPGA', parent_port=True, dir='inout') inst.add_port('I2C_SDA_FPGA', 'I2C_SDA_FPGA', parent_port=True, dir='inout') inst.add_port('I2C_RESET_FPGA', 'I2C_RESET_FPGA', parent_port=True, dir='out') inst.add_port('FAN_CONT_RST_N', 'FAN_CONT_RST_N', parent_port=True, dir='out') inst.add_port('FAN_CONT_ALERT_N', 'FAN_CONT_ALERT_N', parent_port=True, dir='in') inst.add_port('FAN_CONT_FAULT_N', 'FAN_CONT_FAULT_N', parent_port=True, dir='in') inst.add_port('MONITOR_ALERT_N', 'MONITOR_ALERT_N', parent_port=True, dir='in') inst.add_port('MEZZANINE_COMBINED_FAULT', 'MEZZANINE_COMBINED_FAULT', parent_port=True, dir='out') inst.add_port('FPGA_ATX_PSU_KILL', 'FPGA_ATX_PSU_KILL', parent_port=True, dir='out') inst.add_port('USB_FPGA', 'USB_FPGA', parent_port=True, dir='in', width=4) inst.add_port('USB_I2C_CTRL', 'USB_I2C_CTRL', parent_port=True, dir='in') inst.add_port('USB_UART_RXD', 'USB_UART_RXD', parent_port=True, dir='out') inst.add_port('USB_UART_TXD', 'USB_UART_TXD', parent_port=True, dir='in') inst.add_port('PCIE_RST_N', 'PCIE_RST_N', parent_port=True, dir='in') inst.add_port('CPU_PWR_BTN_N', 'CPU_PWR_BTN_N', parent_port=True, dir='out') inst.add_port('CPU_PWR_OK', 'CPU_PWR_OK', parent_port=True, dir='out') inst.add_port('CPU_SYS_RESET_N', 'CPU_SYS_RESET_N', parent_port=True, dir='out') inst.add_port('CPU_SUS_S3_N', 'CPU_SUS_S3_N', parent_port=True, dir='in') inst.add_port('CPU_SUS_S4_N', 'CPU_SUS_S4_N', parent_port=True, dir='in') inst.add_port('CPU_SUS_S5_N', 'CPU_SUS_S5_N', parent_port=True, dir='in') inst.add_port('CPU_SUS_STAT_N', 'CPU_SUS_STAT_N', parent_port=True, dir='in') inst.add_port('EMCCLK', 'EMCCLK', parent_port=True, dir='in') inst.add_port('FPGA_EMCCLK2', 'FPGA_EMCCLK2', parent_port=True, dir='in') inst.add_port('FLASH_DQ', 'FLASH_DQ', parent_port=True, dir='inout', width=16) inst.add_port('FLASH_A', 'FLASH_A', parent_port=True, dir='out', width=29) inst.add_port('FLASH_CS_N', 'FLASH_CS_N', parent_port=True, dir='out') inst.add_port('FLASH_OE_N', 'FLASH_OE_N', parent_port=True, dir='out') inst.add_port('FLASH_WE_N', 'FLASH_WE_N', parent_port=True, dir='out') inst.add_port('FLASH_ADV_N', 'FLASH_ADV_N', parent_port=True, dir='out') inst.add_port('FLASH_RS0', 'FLASH_RS0', parent_port=True, dir='out') inst.add_port('FLASH_RS1', 'FLASH_RS1', parent_port=True, dir='out') inst.add_port('FLASH_WAIT', 'FLASH_WAIT', parent_port=True, dir='in') inst.add_port('SPARTAN_CLK', 'SPARTAN_CLK', parent_port=True, dir='out') inst.add_port('CONFIG_IO_0', 'CONFIG_IO_0', parent_port=True, dir='out') inst.add_port('CONFIG_IO_1', 'CONFIG_IO_1', parent_port=True, dir='out') inst.add_port('CONFIG_IO_2', 'CONFIG_IO_2', parent_port=True, dir='in') inst.add_port('CONFIG_IO_3', 'CONFIG_IO_3', parent_port=True, dir='out') inst.add_port('CONFIG_IO_4', 'CONFIG_IO_4', parent_port=True, dir='out') inst.add_port('CONFIG_IO_5', 'CONFIG_IO_5', parent_port=True, dir='in') inst.add_port('CONFIG_IO_6', 'CONFIG_IO_6', parent_port=True, dir='out') inst.add_port('CONFIG_IO_7', 'CONFIG_IO_7', parent_port=True, dir='out') inst.add_port('CONFIG_IO_8', 'CONFIG_IO_8', parent_port=True, dir='out') inst.add_port('CONFIG_IO_9', 'CONFIG_IO_9', parent_port=True, dir='out') inst.add_port('CONFIG_IO_10', 'CONFIG_IO_10', parent_port=True, dir='out') inst.add_port('CONFIG_IO_11', 'CONFIG_IO_11', parent_port=True, dir='out') inst.add_port('SPI_MISO', 'SPI_MISO', parent_port=True, dir='in') inst.add_port('SPI_MOSI', 'SPI_MOSI', parent_port=True, dir='out') inst.add_port('SPI_CSB', 'SPI_CSB', parent_port=True, dir='out') inst.add_port('SPI_CLK', 'SPI_CLK', parent_port=True, dir='out') inst.add_port('DEBUG_UART_TX', 'DEBUG_UART_TX', parent_port=True, dir='out') inst.add_port('DEBUG_UART_RX', 'DEBUG_UART_RX', parent_port=True, dir='in') # leaving the aux pins here so that we can support them at a later stage. #inst.add_port('AUX_CLK_P', 'AUX_CLK_P', parent_port=True, dir='in') #inst.add_port('AUX_CLK_N', 'AUX_CLK_N', parent_port=True, dir='in') #inst.add_port('AUX_SYNCI_P', 'AUX_SYNCI_P', parent_port=True, dir='in') #inst.add_port('AUX_SYNCI_N', 'AUX_SYNCI_N', parent_port=True, dir='in') #inst.add_port('AUX_SYNCO_P', 'AUX_SYNCO_P', parent_port=True, dir='out') #inst.add_port('AUX_SYNCO_N', 'AUX_SYNCO_N', parent_port=True, dir='out') inst.add_port('EMCCLK_FIX', 'EMCCLK_FIX', parent_port=True, dir='out') inst.add_port('WB_SLV_CLK_I_top', 'wb_clk_i', width=0, dir='out') inst.add_port('WB_SLV_RST_I_top', 'wb_rst_i', width=0, dir='out') inst.add_port('WB_SLV_DAT_I_top', 'wbm_dat_o', width=32, dir='out') inst.add_port('WB_SLV_DAT_O_top', 'wbm_dat_i', width=32, dir='in') inst.add_port('WB_SLV_ACK_O_top', 'wbm_ack_i', width=0, dir='in') inst.add_port('WB_SLV_ADR_I_top', 'wbm_adr_o', width=32, dir='out') inst.add_port('WB_SLV_CYC_I_top', 'wbm_cyc_o', width=0, dir='out') inst.add_port('WB_SLV_SEL_I_top', 'wbm_sel_o', width=4, dir='out') inst.add_port('WB_SLV_STB_I_top', 'wbm_stb_o', width=0, dir='out') inst.add_port('WB_SLV_WE_I_top', 'wbm_we_o', width=0, dir='out') # Need to add ports to tie GPIO control for SKARAB FrontPanelStatus LEDs inst.add_port('dsp_leds_i', 'dsp_leds_i', width=8, dir='in', parent_sig=True) inst.add_port('fpga_leds_o', 'FPGA_LEDS', width=8, dir='out', parent_port=True)
#inst.add_port('fabric_clk_270', 'adc0_clk270') #top.add_signal('adc0_clk')
[docs] def gen_children(self): return [ YellowBlock.make_block({'fullpath': self.fullpath, 'tag': 'xps:sys_block', 'board_id': '3', 'rev_maj': '2', 'rev_min': '0', 'rev_rcs': '1','scratchpad': '0'}, self.platform) #YellowBlock.make_block({'tag': 'xps:forty_gbe'}, self.platform) ]
[docs] def gen_constraints(self): cons = [ RawConstraint('set_property CONFIG_MODE BPI16 [current_design]'), RawConstraint('set_property CONFIG_VOLTAGE %.1f [current_design]' % self.platform.conf['config_voltage']), RawConstraint('set_property CFGBVS %s [current_design]' % self.platform.conf['cfgbvs']), RawConstraint('set_property BITSTREAM.STARTUP.STARTUPCLK CCLK [current_design]'), RawConstraint('set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]'), RawConstraint('set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]'), RawConstraint('set_property BITSTREAM.CONFIG.TIMER_CFG 0X00040000 [current_design]')] if self.platform.boot_image == 'golden': cons.append(RawConstraint('set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]')) cons.append(RawConstraint('set_property BITSTREAM.CONFIG.BPI_SYNC_MODE DISABLE [current_design]')) else: cons.append(RawConstraint('set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-2 [current_design]')) cons.append(RawConstraint('set_property BITSTREAM.CONFIG.BPI_SYNC_MODE TYPE1 [current_design]')) cons.append(PortConstraint('FLASH_DQ', 'FLASH_DQ', port_index=list(range(16)), iogroup_index=list(range(16)))) cons.append(PortConstraint('USB_FPGA', 'USB_FPGA', port_index=list(range( 4)), iogroup_index=list(range( 4)))) cons.append(PortConstraint('FLASH_A', 'FLASH_A', port_index=list(range(29)), iogroup_index=list(range(29)))) cons.append(PortConstraint('GND', 'GND', port_index=list(range(16)), iogroup_index=list(range(16)))) cons.append(PortConstraint('ONE_GBE_INT_N', 'ONE_GBE_INT_N')) cons.append(PortConstraint('FPGA_RESET_N', 'FPGA_RESET_N')) cons.append(PortConstraint('FLASH_WE_N', 'FLASH_WE_N')) cons.append(PortConstraint('FPGA_EMCCLK2', 'FPGA_EMCCLK2')) cons.append(PortConstraint('MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N','MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(PortConstraint('MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N','MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(PortConstraint('MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N','MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(PortConstraint('MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N','MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(PortConstraint('MEZZANINE_3_SCL_FPGA','MEZZANINE_3_SCL_FPGA')) cons.append(PortConstraint('MEZZANINE_2_SCL_FPGA','MEZZANINE_2_SCL_FPGA')) cons.append(PortConstraint('MEZZANINE_1_SCL_FPGA','MEZZANINE_1_SCL_FPGA')) cons.append(PortConstraint('MEZZANINE_0_SCL_FPGA','MEZZANINE_0_SCL_FPGA')) cons.append(PortConstraint('EMCCLK_FIX','EMCCLK_FIX')) cons.append(PortConstraint('ONE_WIRE_EEPROM','ONE_WIRE_EEPROM')) cons.append(PortConstraint('I2C_SCL_FPGA','I2C_SCL_FPGA')) cons.append(PortConstraint('FPGA_REFCLK_BUF0_P','FPGA_REFCLK_BUF0_P')) cons.append(PortConstraint('FPGA_REFCLK_BUF0_N','FPGA_REFCLK_BUF0_N')) cons.append(PortConstraint('ONE_GBE_LINK','ONE_GBE_LINK')) cons.append(PortConstraint('SPI_CLK','SPI_CLK')) cons.append(PortConstraint('MEZZANINE_3_INT_N','MEZZANINE_3_INT_N')) cons.append(PortConstraint('MEZZANINE_2_INT_N','MEZZANINE_2_INT_N')) cons.append(PortConstraint('MEZZANINE_1_INT_N','MEZZANINE_1_INT_N')) cons.append(PortConstraint('MEZZANINE_0_INT_N','MEZZANINE_0_INT_N')) cons.append(PortConstraint('SPI_MISO','SPI_MISO')) cons.append(PortConstraint('MEZZANINE_3_PRESENT_N','MEZZANINE_3_PRESENT_N')) cons.append(PortConstraint('MEZZANINE_2_PRESENT_N','MEZZANINE_2_PRESENT_N')) cons.append(PortConstraint('MEZZANINE_1_PRESENT_N','MEZZANINE_1_PRESENT_N')) cons.append(PortConstraint('MEZZANINE_0_PRESENT_N','MEZZANINE_0_PRESENT_N')) cons.append(PortConstraint('SPI_CSB','SPI_CSB')) cons.append(PortConstraint('FPGA_REFCLK_BUF1_P','FPGA_REFCLK_BUF1_P')) cons.append(PortConstraint('FPGA_REFCLK_BUF1_N','FPGA_REFCLK_BUF1_N')) cons.append(PortConstraint('PCIE_RST_N','PCIE_RST_N')) cons.append(PortConstraint('SPI_MOSI','SPI_MOSI')) cons.append(PortConstraint('USB_I2C_CTRL','USB_I2C_CTRL')) cons.append(PortConstraint('DEBUG_UART_RX','DEBUG_UART_RX')) cons.append(PortConstraint('USB_UART_RXD','USB_UART_RXD')) cons.append(PortConstraint('FAN_CONT_RST_N','FAN_CONT_RST_N')) cons.append(PortConstraint('CPU_SUS_S3_N','CPU_SUS_S3_N')) cons.append(PortConstraint('MEZZANINE_COMBINED_FAULT','MEZZANINE_COMBINED_FAULT')) cons.append(PortConstraint('EMCCLK','EMCCLK')) cons.append(PortConstraint('MONITOR_ALERT_N','MONITOR_ALERT_N')) cons.append(PortConstraint('I2C_RESET_FPGA','I2C_RESET_FPGA')) cons.append(PortConstraint('I2C_SDA_FPGA','I2C_SDA_FPGA')) cons.append(PortConstraint('MEZZANINE_3_FAULT_N','MEZZANINE_3_FAULT_N')) cons.append(PortConstraint('MEZZANINE_2_FAULT_N','MEZZANINE_2_FAULT_N')) cons.append(PortConstraint('MEZZANINE_1_FAULT_N','MEZZANINE_1_FAULT_N')) cons.append(PortConstraint('MEZZANINE_0_FAULT_N','MEZZANINE_0_FAULT_N')) cons.append(PortConstraint('FAN_CONT_ALERT_N','FAN_CONT_ALERT_N')) cons.append(PortConstraint('FLASH_CS_N','FLASH_CS_N')) cons.append(PortConstraint('ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N','ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N')) cons.append(PortConstraint('CPU_SUS_STAT_N','CPU_SUS_STAT_N')) cons.append(PortConstraint('USB_UART_TXD','USB_UART_TXD')) cons.append(PortConstraint('FLASH_ADV_N','FLASH_ADV_N')) cons.append(PortConstraint('FAN_CONT_FAULT_N','FAN_CONT_FAULT_N')) cons.append(PortConstraint('CPU_PWR_OK','CPU_PWR_OK')) cons.append(PortConstraint('MEZZANINE_3_ENABLE_N','MEZZANINE_3_ENABLE_N')) cons.append(PortConstraint('MEZZANINE_2_ENABLE_N','MEZZANINE_2_ENABLE_N')) cons.append(PortConstraint('MEZZANINE_1_ENABLE_N','MEZZANINE_1_ENABLE_N')) cons.append(PortConstraint('MEZZANINE_0_ENABLE_N','MEZZANINE_0_ENABLE_N')) cons.append(PortConstraint('DEBUG_UART_TX','DEBUG_UART_TX')) cons.append(PortConstraint('SPARTAN_CLK','SPARTAN_CLK')) cons.append(PortConstraint('MEZZANINE_3_RESET','MEZZANINE_3_RESET')) cons.append(PortConstraint('MEZZANINE_3_SDA_FPGA','MEZZANINE_3_SDA_FPGA')) cons.append(PortConstraint('MEZZANINE_2_SDA_FPGA','MEZZANINE_2_SDA_FPGA')) cons.append(PortConstraint('MEZZANINE_1_SDA_FPGA','MEZZANINE_1_SDA_FPGA')) cons.append(PortConstraint('MEZZANINE_0_SDA_FPGA','MEZZANINE_0_SDA_FPGA')) cons.append(PortConstraint('CPU_SUS_S4_N','CPU_SUS_S4_N')) cons.append(PortConstraint('FLASH_WAIT','FLASH_WAIT')) cons.append(PortConstraint('FPGA_ATX_PSU_KILL','FPGA_ATX_PSU_KILL')) cons.append(PortConstraint('CPU_PWR_BTN_N','CPU_PWR_BTN_N')) cons.append(PortConstraint('FLASH_OE_N','FLASH_OE_N')) cons.append(PortConstraint('MEZZANINE_3_ONE_WIRE','MEZZANINE_3_ONE_WIRE')) cons.append(PortConstraint('MEZZANINE_2_ONE_WIRE','MEZZANINE_2_ONE_WIRE')) cons.append(PortConstraint('MEZZANINE_1_ONE_WIRE','MEZZANINE_1_ONE_WIRE')) cons.append(PortConstraint('MEZZANINE_0_ONE_WIRE','MEZZANINE_0_ONE_WIRE')) cons.append(PortConstraint('FLASH_RS1','FLASH_RS1')) cons.append(PortConstraint('FLASH_RS0','FLASH_RS0')) cons.append(PortConstraint('CPU_SYS_RESET_N','CPU_SYS_RESET_N')) cons.append(PortConstraint('MEZZANINE_3_CLK_SEL','MEZZANINE_3_CLK_SEL')) cons.append(PortConstraint('CPU_SUS_S5_N','CPU_SUS_S5_N')) cons.append(PortConstraint('CONFIG_IO_0','CONFIG_IO_0')) cons.append(PortConstraint('CONFIG_IO_1','CONFIG_IO_1')) cons.append(PortConstraint('CONFIG_IO_2','CONFIG_IO_2')) cons.append(PortConstraint('CONFIG_IO_3','CONFIG_IO_3')) cons.append(PortConstraint('CONFIG_IO_4','CONFIG_IO_4')) cons.append(PortConstraint('CONFIG_IO_5','CONFIG_IO_5')) cons.append(PortConstraint('CONFIG_IO_6','CONFIG_IO_6')) cons.append(PortConstraint('CONFIG_IO_7','CONFIG_IO_7')) cons.append(PortConstraint('CONFIG_IO_8','CONFIG_IO_8')) cons.append(PortConstraint('CONFIG_IO_9','CONFIG_IO_9')) cons.append(PortConstraint('CONFIG_IO_10','CONFIG_IO_10')) cons.append(PortConstraint('CONFIG_IO_11','CONFIG_IO_11')) # - Front Panel LED constraints cons.append(PortConstraint(portname='FPGA_LEDS', iogroup='led', port_index=list(range(8)), iogroup_index=list(range(8)))) cons.append(MaxDelayConstraint(destpath='[get_ports {FPGA_LEDS[*]}]', constdelay_ns=1.0)) cons.append(MinDelayConstraint(destpath='[get_ports {FPGA_LEDS[*]}]', constdelay_ns=1.0)) cons.append(FalsePathConstraint(destpath='[get_ports {FPGA_LEDS[*]}]')) #Clock Constraints #cons.append(RawConstraint('create_clock -period 2.800 -name AUX_CLK_P -waveform {0.000 1.400} [get_ports AUX_CLK_P]')) cons.append(ClockConstraint('FPGA_REFCLK_BUF0_P','FPGA_REFCLK_BUF0_P', period=6.4, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=3.2)) cons.append(ClockConstraint('FPGA_REFCLK_BUF1_P','FPGA_REFCLK_BUF1_P', period=6.4, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=3.2)) cons.append(ClockConstraint('FPGA_EMCCLK2','FPGA_EMCCLK2', period=16.666, port_en=True, virtual_en=False, waveform_min=0.000, waveform_max=8.333)) #cons.append(ClockConstraint(name='VIRTUAL_clkout0', period=8.0, port_en=False, virtual_en=True, waveform_min=0.0, waveform_max=4.0)) #cons.append(ClockConstraint(name='VIRTUAL_clkout0_1', period=6.4, port_en=False, virtual_en=True, waveform_min=0.0, waveform_max=3.2)) #cons.append(ClockConstraint(name='virtual_clock', period=6.4, port_en=False, virtual_en=True, waveform_min=0.0, waveform_max=3.2)) #cons.append(ClockConstraint(name='VIRTUAL_I', period=self.clkparams[3], port_en=False, virtual_en=True, waveform_min=0.0, waveform_max=self.clkparams[4])) cons.append(ClockConstraint(name='virtual_emcc_clock', period=16.666, port_en=False, virtual_en=True, waveform_min=0.0, waveform_max=8.333)) #Generate Clock Constraints #cons.append(GenClockConstraint(signal='%s/wishbone_flash_sdram_interface_0/icape_controller_0/icape_clk_count_reg[3]/Q' % self.fullname, name='%s/wishbone_flash_sdram_interface_0/icape_controller_0/CLK' % self.fullname, divide_by=16, clock_source='%s/wishbone_flash_sdram_interface_0/icape_controller_0/icape_clk_count_reg[3]/C' % self.fullname)) #Clock Group Constraints cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'FPGA_EMCCLK2', 'asynchronous')) #cons.append(ClockGroupConstraint('%s/wishbone_flash_sdram_interface_0/icape_controller_0/CLK' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) #cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '%s/wishbone_flash_sdram_interface_0/icape_controller_0/CLK' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'FPGA_EMCCLK2', 'asynchronous')) cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) #cons.append(ClockGroupConstraint('-include_generated_clocks FPGA_REFCLK_BUF1_P', '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous')) #cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous')) cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous')) cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'FPGA_EMCCLK2', 'asynchronous')) #Input Constraints cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=3.0, add_delay_en=True, portname='FLASH_DQ[*]')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FLASH_DQ[*]')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='USB_FPGA[*]')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='USB_FPGA[*]')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_2')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_2')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_5')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_5')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='DEBUG_UART_RX')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='DEBUG_UART_RX')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FAN_CONT_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FAN_CONT_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FAN_CONT_ALERT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FAN_CONT_ALERT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='FPGA_EMCCLK2', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='FPGA_EMCCLK2', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='I2C_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='I2C_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='I2C_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='I2C_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_FAULT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_ONE_WIRE')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_PRESENT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_SCL_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_SDA_FPGA')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MONITOR_ALERT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MONITOR_ALERT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='ONE_WIRE_EEPROM')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='ONE_WIRE_EEPROM')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='SPI_MISO')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='SPI_MISO')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='USB_I2C_CTRL')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='USB_I2C_CTRL')) cons.append(InputDelayConstraint(clkname='virtual_emcc_clock', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='EMCCLK')) cons.append(InputDelayConstraint(clkname='virtual_emcc_clock', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='EMCCLK')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='USB_UART_TXD')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='USB_UART_TXD')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='ONE_GBE_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='ONE_GBE_INT_N')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='ONE_GBE_LINK')) cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='ONE_GBE_LINK')) #cons.append(InputDelayConstraint(clkname='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N')) #cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N')) # Output Constraints cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_A[*]')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_A[*]')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_DQ[*]')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_DQ[*]')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_ADV_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_ADV_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_CS_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_CS_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_OE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_OE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_RS0')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_RS0')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_RS1')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_RS1')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='FLASH_WE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='FLASH_WE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=-2.5, add_delay_en=True, portname='SPARTAN_CLK')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='SPARTAN_CLK')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_0')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_0')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_1')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_1')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_3')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_3')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_4')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_4')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_6')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_6')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_7')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_7')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_8')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_8')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_9')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_9')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_10')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_10')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='CONFIG_IO_11')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='CONFIG_IO_11')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='DEBUG_UART_TX')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='DEBUG_UART_TX')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_ATX_PSU_KILL')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_ATX_PSU_KILL')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='I2C_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='I2C_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='I2C_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='I2C_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_0_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_0_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_1_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_1_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_2_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_2_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_CLK_SEL')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_CLK_SEL')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_ENABLE_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_ONE_WIRE')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_RESET')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_RESET')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_SCL_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_3_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_3_SDA_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='MEZZANINE_COMBINED_FAULT')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='MEZZANINE_COMBINED_FAULT')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='ONE_WIRE_EEPROM')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='ONE_WIRE_EEPROM')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='SPI_CLK')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='SPI_CLK')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='SPI_CSB')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='SPI_CSB')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='SPI_MOSI')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='SPI_MOSI')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='USB_UART_RXD')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='USB_UART_RXD')) cons.append(OutputDelayConstraint(clkname='virtual_emcc_clock', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='EMCCLK_FIX')) cons.append(OutputDelayConstraint(clkname='virtual_emcc_clock', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='EMCCLK_FIX')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FAN_CONT_RST_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FAN_CONT_RST_N')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='I2C_RESET_FPGA')) cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='I2C_RESET_FPGA')) #False Path Constraints #cons.append(FalsePathConstraint(destpath='[get_pins {%s/FPGA_DNA_CHECKER_inst/FPGA_DNA_O_reg[*]/D}]' % self.fullname)) #cons.append(FalsePathConstraint(destpath='[get_pins {%s/clock_frequency_measure_1/second_toggle_z_reg/D}]' % self.fullname)) #cons.append(FalsePathConstraint(destpath='[get_pins {%s/clock_frequency_measure_1/clk_count_low_reg_reg[*]/D}]' % self.fullname)) #cons.append(FalsePathConstraint(destpath='[get_pins {%s/clock_frequency_measure_1/clk_count_high_reg_reg[*]/D}]' % self.fullname)) #cons.append(FalsePathConstraint(destpath='[get_pins {%s/clock_frequency_measure_2/second_toggle_z_reg/D}]' % self.fullname)) #cons.append(FalsePathConstraint(destpath='[get_pins {%s/clock_frequency_measure_2/clk_count_low_reg_reg[*]/D}]' % self.fullname)) #cons.append(FalsePathConstraint(destpath='[get_pins {%s/clock_frequency_measure_2/clk_count_high_reg_reg[*]/D}]' % self.fullname)) #Multi Cycle Constraints #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks FPGA_REFCLK_BUF0_P', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks FPGA_REFCLK_BUF0_P', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks virtual_clock', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks virtual_clock', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks VIRTUAL_clkout0', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks VIRTUAL_clkout0', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks FPGA_EMCCLK2', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks FPGA_EMCCLK2', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ENABLE_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ENABLE_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ONE_WIRE', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ONE_WIRE', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_ENABLE_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_ENABLE_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_ONE_WIRE', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_ONE_WIRE', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_ENABLE_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_ENABLE_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_ONE_WIRE', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_ONE_WIRE', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports CONFIG_IO_10', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports CONFIG_IO_10', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports CONFIG_IO_11', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports CONFIG_IO_11', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports DEBUG_UART_TX', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports DEBUG_UART_TX', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports FPGA_ATX_PSU_KILL', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports FPGA_ATX_PSU_KILL', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports I2C_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports I2C_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports I2C_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports I2C_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_0_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_0_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_0_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_0_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_0_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_0_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_0_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_0_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_1_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_1_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_1_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_1_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_1_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_1_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_1_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_1_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_1_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_2_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_2_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_2_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_2_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_2_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_clkout0_1', destpath='get_ports MEZZANINE_2_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_2_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks VIRTUAL_I', destpath='get_ports MEZZANINE_2_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_2_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_CLK_SEL', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_CLK_SEL', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_ENABLE_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_ENABLE_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_ONE_WIRE', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_ONE_WIRE', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_RESET', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_RESET', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_SCL_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_SCL_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_SDA_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_3_SDA_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_COMBINED_FAULT', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_COMBINED_FAULT', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports ONE_WIRE_EEPROM', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports ONE_WIRE_EEPROM', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports SPI_CLK', multicycledelay=2)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports SPI_CLK', multicycledelay=1)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports SPI_CSB', multicycledelay=2)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports SPI_CSB', multicycledelay=1)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports SPI_MOSI', multicycledelay=2)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports SPI_MOSI', multicycledelay=1)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports USB_UART_RXD', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports USB_UART_RXD', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks virtual_clock', destpath='get_ports EMCCLK_FIX', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks virtual_clock', destpath='get_ports EMCCLK_FIX', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports FAN_CONT_RST_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports FAN_CONT_RST_N', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks virtual_clock', destpath='get_ports I2C_RESET_FPGA', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks virtual_clock', destpath='get_ports I2C_RESET_FPGA', multicycledelay=3)) #cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks virtual_clock', destpath='get_ports ONE_GBE_RESET_N', multicycledelay=4)) #cons.append(MultiCycleConstraint(multicycletype='hold' ,sourcepath='get_clocks virtual_clock', destpath='get_ports ONE_GBE_RESET_N', multicycledelay=3)) #cons.append(RawConstraint('set_clock_groups -asynchronous -group [get_clocks AUX_CLK_P] -group [get_clocks FPGA_REFCLK_BUF0_P]')) #cons.append(RawConstraint('set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks AUX_CLK_P]')) #Raw Constraints #fortygbefullname = self.fullpath.replace('/', '_') cons.append(RawConstraint('set_property LOC ICAP_X0Y1 [get_cells '+self.fullname+'/wishbone_flash_sdram_interface_0/icape_controller_0/ICAPE2_0]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_0]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_1]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_10]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_11]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_3]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_4]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_6]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_7]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_8]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CONFIG_IO_9]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CPU_PWR_BTN_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CPU_PWR_OK]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports CPU_SYS_RESET_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports DEBUG_UART_TX]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FAN_CONT_RST_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_ADV_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[0]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[10]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[11]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[12]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[13]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[14]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[15]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[16]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[17]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[18]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[19]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[1]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[20]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[21]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[22]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[23]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[24]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[25]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[26]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[27]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[28]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[2]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[3]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[4]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[5]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[6]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[7]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[8]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_A[9]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_CS_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[0]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[10]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[11]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[12]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[13]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[14]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[15]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[1]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[2]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[3]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[4]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[5]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[6]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[7]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[8]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_DQ[9]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_OE_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_RS0]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_RS1]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FLASH_WE_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_ATX_PSU_KILL]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[0]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[10]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[11]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[12]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[13]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[14]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[15]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[1]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[2]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[3]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[4]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[5]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[6]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[7]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[8]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports GND[9]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports I2C_RESET_FPGA]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports I2C_SCL_FPGA]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports I2C_SDA_FPGA]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_0_CLK_SEL]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_0_ENABLE_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_0_ONE_WIRE]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_0_ONE_WIRE_STRONG_PULLUP_EN_N]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_0_RESET]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_1_CLK_SEL]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_1_ENABLE_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_1_ONE_WIRE]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_1_ONE_WIRE_STRONG_PULLUP_EN_N]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_1_RESET]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_2_CLK_SEL]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_2_ENABLE_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_2_ONE_WIRE]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_2_ONE_WIRE_STRONG_PULLUP_EN_N]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_2_RESET]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_3_CLK_SEL]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_3_ENABLE_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_3_ONE_WIRE]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_3_ONE_WIRE_STRONG_PULLUP_EN_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports MEZZANINE_3_RESET]')) #cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports ONE_GBE_RESET_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports ONE_WIRE_EEPROM]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports ONE_WIRE_EEPROM_STRONG_PULLUP_EN_N]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports SPARTAN_CLK]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports SPI_CLK]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports SPI_CSB]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports USB_UART_RXD]')) # For the Front Panel LEDs cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[0]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[1]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[2]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[3]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[4]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[5]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[6]]')) cons.append(RawConstraint('set_property OFFCHIP_TERM NONE [get_ports FPGA_LEDS[7]]')) return cons
[docs] def gen_tcl_cmds(self): tcl_cmds = [] tcl_cmds.append('set_property SCOPED_TO_REF cont_microblaze [get_files [get_property directory [current_project]]/myproj.srcs/sources_1/imports/cont_microblaze/EMB123701U1R1.elf]') tcl_cmds.append('set_property SCOPED_TO_REF cont_microblaze [get_files [get_property directory [current_project]]/myproj.gen/sources_1/bd/cont_microblaze/cont_microblaze.bmm]') tcl_cmds.append('set_property SCOPED_TO_CELLS microblaze_0 [get_files [get_property directory [current_project]]/myproj.srcs/sources_1/imports/cont_microblaze/EMB123701U1R1.elf]') tcl_cmds.append('import_files -force -fileset constrs_1 %s/skarab_infr/Constraints/soc_version.xdc'%os.getenv('HDL_ROOT')) #Allows the microblaze to be edited tcl_cmds.append('set_property ip_repo_paths %s/skarab_infr/cont_microblaze/ipshared/peralex.com/ [current_project]'%os.getenv('HDL_ROOT')) #tcl_cmds.append('update_ip_catalog') return {'pre_synth': tcl_cmds}