CASPER Toolflow

Setup

  • Installing the Toolflow
    • Getting the right versions
    • Pre-requisites
    • Obtaining the Toolflow
    • Configuring the toolflow
  • How to install MATLAB
    • [Current Vivado flow] How To install R2021a
    • [Current Vivado Flow] How to install R2022a
    • [ISE legacy flow, ROACH2] How to install R2013b
  • How to install Xilinx Tools
    • [Current Vivado flow] How to install 2021.1
      • Optional: Install USB Drivers for JTAG
    • [Current Vivado flow] How to install 2023.1
    • [ISE legacy flow, ROACH2] How to install Xilinx ISE
      • Tweaks for Ubuntu 16.04
  • How to install casperfpga
    • Installing casperfpga using a virtual environment
      • Testing that the installation worked
    • Using casperfpga
    • Contributing towards casperfpga
  • Configuring the Toolflow
    • The startsg script
      • Specifying local details
      • Using startsg
      • Symlink for convenience
  • Running the Toolflow
    • MATLAB/Python method
      • jasper_frontend:
      • jasper:
    • Python method
      • Running the command

Documentation

  • CASPER Tutorials
  • AXI Documentation
    • 1. Introduction
    • 2. AXI4-Lite Interface
    • 3. AXI4-Lite Transactions
      • a. Read Transactions
      • b. Write Transactions
    • 4. AXI4-Lite Interface Signals
    • 5. Custom AXI4-Lite Interface
      • a. sys_block
      • b. Software Register
      • c. BRAM
      • d. Raw AXI4-Lite Interface
        • i. Simulink Block
        • ii Yellow Block Python Script (raw_axi.py)
        • iii Creating hdl Source Code
    • 6. XML File Generation
  • Block Documentation
    • Signal Processing Blocks
      • Adder Tree
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Barrel Switcher
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Bit Reverser
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Conjugate Complex 4-bit Multiplier BRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Complex 4-bit Multiplier BRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Conjugate Complex 4-bit Multiplier, Dedicated Multipliers
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Complex 4-bit Multiplier, Embedded Multipliers
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Conjugate Complex 4-bit Multiplier, Slices
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Complex 4-bit Multiplier, Slices
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Complex Adder/Subtractor
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Complex to Real-Imag
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • DDS
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Decimating FIR Filter
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Enabled Delay in BRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Programmable Delay in BRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Delay in BRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Complex Delay
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Delay in Slices
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Programmable Wideband Delay
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • DRAM Vector Accumulator
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • DRAM Vector Accumulator Test Vector Generator
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Edge Detect
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Real-sampled Biplex FFT (demuxed by 2)
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Real-sampled Biplex FFT (demuxed by 4)
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • FFT
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Real-sampled Wideband FFT
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Programmable Fine Delay w/ Fringe stop
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Programmable Fine Delay w/ Fringe stop, CORDIC
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • FIR Column
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • FIR Double Column
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • FIR Tap
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Freeze Counter Block
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Local Oscillator Constant
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Local Oscillator
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Mixer
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Negative Edge Detect
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Partial Delay
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Polyphase Real FIR Filter
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Polyphase FIR Filter
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Positive Edge Detect
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Power
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Pulse Extender
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • RC Multiplier
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Reorder
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Real-Imag to Complex
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Square Transposer
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Stopwatch
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Enabled Sync Delay
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Programmable Sync Delay
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Sync Pulse Generator
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Windowed X-Engine
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • X-Engine TVG
        • Summary
        • Mask Parameters
        • Ports
        • Description
    • Communication Blocks
      • 10 GbE Transceiver
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • XAUI
        • Summary
        • Mask Parameters
        • Ports
        • Description
    • System Blocks
      • ADC
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • X64 ADC
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • 64ADCx64-12
      • DAC
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • DRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Bi-directional GPIO
        • Summary
        • Mask Parameters
        • Ports
        • Notes
      • GPIO
        • Summary
        • Mask Parameters
        • Ports
        • Description
        • Notes
      • QDR
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Snapshot
        • Summary
        • Mask Parameters
        • Ports
        • Software interface
        • Description
      • Snapshot Capture
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • 64 Bit Snapshot
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Software Register
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • SRAM
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • XSG Core Config
        • Summary
        • Mask Parameters
        • Ports
        • Description
      • Gaussian Random Number Generator
        • Summary
        • Ports
        • Description
        • Test Results
      • Correlation Control Block
        • Summary
        • Ports
        • Description
        • Test Results
  • The CASPER Toolflow
    • Goals of the CASPER Toolflow
    • Toolflow Terminology
    • Parts of the Toolflow
      • Peripherals file
      • Platforms
      • The VerilogModule Class
      • Yellow Blocks
    • How it all fits together
    • Supporting New Hardware
      • Adding a New Platform
        • Adding a Platform to the Toolflow Frontend
        • Adding a Platform to the Toolflow Middleware
        • Compiling
      • Adding a New Peripheral
  • Toolflow Sourcecode
    • castro
      • Castro
        • Castro.__init__()
        • Castro.dump()
        • Castro.load()
      • ClkConstraint
        • ClkConstraint.__init__()
      • ClkGrpConstraint
        • ClkGrpConstraint.__init__()
      • FalsePthConstraint
        • FalsePthConstraint.__init__()
      • GenClkConstraint
        • GenClkConstraint.__init__()
      • InDelayConstraint
        • InDelayConstraint.__init__()
      • MaxDelayConstraint
        • MaxDelayConstraint.__init__()
      • MinDelayConstraint
        • MinDelayConstraint.__init__()
      • MultiCycConstraint
        • MultiCycConstraint.__init__()
      • OutDelayConstraint
        • OutDelayConstraint.__init__()
      • PinConstraint
        • PinConstraint.__init__()
      • RawConstraint
        • RawConstraint.__init__()
      • Synthesis
        • Synthesis.__init__()
        • Synthesis.resolve_constraint()
      • mm_slave
        • mm_slave.__init__()
    • constraints
      • ClockConstraint
        • ClockConstraint.__init__()
      • ClockGroupConstraint
        • ClockGroupConstraint.__init__()
      • FalsePathConstraint
        • FalsePathConstraint.__init__()
      • GenClockConstraint
        • GenClockConstraint.__init__()
      • InputDelayConstraint
        • InputDelayConstraint.__init__()
      • MaxDelayConstraint
        • MaxDelayConstraint.__init__()
      • MinDelayConstraint
        • MinDelayConstraint.__init__()
      • MultiCycleConstraint
        • MultiCycleConstraint.__init__()
      • OutputDelayConstraint
        • OutputDelayConstraint.__init__()
      • PortConstraint
        • PortConstraint.__init__()
        • PortConstraint.gen_physical_const()
      • RawConstraint
        • RawConstraint.__init__()
    • exec_flow
    • helpers
      • to_int_list()
      • write_file()
    • memory
      • Register
        • Register.__init__()
    • platform
      • architecture()
      • freedesktop_os_release()
      • java_ver()
      • libc_ver()
      • mac_ver()
      • machine()
      • node()
      • platform()
      • processor()
      • python_branch()
      • python_build()
      • python_compiler()
      • python_implementation()
      • python_revision()
      • python_version()
      • python_version_tuple()
      • release()
      • system()
      • system_alias()
      • uname()
      • uname_result
        • uname_result.processor
      • version()
      • win32_edition()
      • win32_is_iot()
      • win32_ver()
    • toolflow
    • verilog
      • AXI4LiteDevice
        • AXI4LiteDevice.__init__()
        • AXI4LiteDevice.base_addr
        • AXI4LiteDevice.high_addr
      • ImmutableWithComments
        • ImmutableWithComments.__init__()
      • Parameter
        • Parameter.__init__()
        • Parameter.update_attrs()
      • Port
        • Port.__init__()
        • Port.update_attrs()
      • Signal
        • Signal.__init__()
        • Signal.update_attrs()
      • VerilogModule
        • VerilogModule.__init__()
        • VerilogModule.add_axi4lite_interface()
        • VerilogModule.add_axi_interface()
        • VerilogModule.add_localparam()
        • VerilogModule.add_parameter()
        • VerilogModule.add_port()
        • VerilogModule.add_raw_string()
        • VerilogModule.add_rfdc_interface()
        • VerilogModule.add_signal()
        • VerilogModule.add_sourcefile()
        • VerilogModule.add_wb_interface()
        • VerilogModule.add_xil_axi4lite_interface()
        • VerilogModule.assign_signal()
        • VerilogModule.assign_wb_interface()
        • VerilogModule.axi4lite_memory_map()
        • VerilogModule.gen_assignments_ascii_art()
        • VerilogModule.gen_assignments_str()
        • VerilogModule.gen_cur_blk_comment()
        • VerilogModule.gen_default_nettype_str()
        • VerilogModule.gen_endmod_str()
        • VerilogModule.gen_instance_verilog()
        • VerilogModule.gen_instances_ascii_art()
        • VerilogModule.gen_instances_dec_str()
        • VerilogModule.gen_localparams_dec_str()
        • VerilogModule.gen_mod_dec_str()
        • VerilogModule.gen_module_file()
        • VerilogModule.gen_params_dec_str()
        • VerilogModule.gen_port_list()
        • VerilogModule.gen_ports_dec_str()
        • VerilogModule.gen_signals_ascii_art()
        • VerilogModule.gen_signals_dec_str()
        • VerilogModule.gen_top_mod()
        • VerilogModule.get_base_wb_slaves()
        • VerilogModule.get_instance()
        • VerilogModule.has_instance()
        • VerilogModule.instantiate_child_ports()
        • VerilogModule.rewrite_module_file()
        • VerilogModule.search_dict_for_name()
        • VerilogModule.set_cur_blk()
        • VerilogModule.wb_compute()
        • VerilogModule.write_new_module_file()
      • WbDevice
        • WbDevice.__init__()
        • WbDevice.base_addr
        • WbDevice.high_addr
        • WbDevice.sub_arb_id
      • gen_wbs_master_arbiter()
      • instantiate_wb_arb_module()
      • wrap_instance()
    • yellow_blocks
      • adc
        • adc
      • adc16
        • adc16
      • adc20g
        • adc20g
      • adc5g
        • adc5g
      • bram
        • bram
      • clock_passthrough
        • clock_passthrough
      • dcp
        • dcp
      • forty_gbe
        • forty_gbe
        • fortygbe_main
        • fortygbe_skarab
      • gpio
        • gpio
      • gpio_bidir
        • gpio_bidir
      • hmc
        • hmc
      • i2c_interface
        • i2c_interface
      • ip
        • ip
      • lmx2581
        • lmx2581
      • microblaze
        • microblaze
        • microblaze_k7
        • microblaze_ku7
        • microblaze_vu_plus
      • onegbe
        • onegbe
        • onegbe_casia_k7
        • onegbe_skarab
        • onegbe_snap
        • onegbe_vcu118
        • onegbe_vcu128
      • skarab
        • skarab
      • snap
        • snap
      • snap2
        • snap2
      • snap_adc
        • snap_adc
      • spi_wb_bridge
        • spi_wb_bridge
      • sw_reg
        • sw_reg
      • sw_reg_sync
        • sw_reg_sync
      • sys_block
        • sys_block
      • ten_gbe
        • ten_gbe
        • tengbaser_xilinx_k7
        • tengbaser_xilinx_ku7
        • tengbaser_xilinx_ultrascale
        • tengbaser_xilinx_usplus
        • tengbe_v2_xilinx_v6
      • vcu118
        • vcu118
      • xadc
        • xadc
      • xsg
        • xsg
      • yellow_block
        • YellowBlock
      • yellow_block_typecodes
  • casperfpga Sourcecode
CASPER Toolflow
  • Overview: module code

All modules for which code is available

  • castro
  • constraints
  • helpers
  • memory
  • platform
  • verilog
  • yellow_blocks.adc
  • yellow_blocks.adc16
  • yellow_blocks.adc20g
  • yellow_blocks.adc5g
  • yellow_blocks.bram
  • yellow_blocks.clock_passthrough
  • yellow_blocks.dcp
  • yellow_blocks.forty_gbe
  • yellow_blocks.gpio
  • yellow_blocks.gpio_bidir
  • yellow_blocks.hmc
  • yellow_blocks.i2c_interface
  • yellow_blocks.ip
  • yellow_blocks.lmx2581
  • yellow_blocks.microblaze
  • yellow_blocks.onegbe
  • yellow_blocks.skarab
  • yellow_blocks.snap
  • yellow_blocks.snap2
  • yellow_blocks.snap_adc
  • yellow_blocks.spi_wb_bridge
  • yellow_blocks.sw_reg
  • yellow_blocks.sw_reg_sync
  • yellow_blocks.sys_block
  • yellow_blocks.ten_gbe
  • yellow_blocks.vcu118
  • yellow_blocks.xadc
  • yellow_blocks.xsg
  • yellow_blocks.yellow_block

© Copyright 2018, Collaboration for Astronomy Signal Processing and Electronics Research.

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